1. 30 10月, 2012 1 次提交
  2. 21 6月, 2012 1 次提交
  3. 13 5月, 2012 1 次提交
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      SPEAr: clk: Add VCO-PLL Synthesizer clock · 55b8fd4f
      Viresh Kumar 提交于
      All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations
      
      - In normal mode
        vco = (2 * M[15:8] * Fin)/N
      
      - In Dithered mode
        vco = (2 * M[15:0] * Fin)/(256 * N)
      
      pll_rate = vco/2^p
      
      vco and pll are very closely bound to each other,
      "vco needs to program: mode, m & n" and "pll needs to program p",
      both share common enable/disable logic and registers.
      
      This patch adds in support for this type of clock.
      Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
      Reviewed-by: NMike Turquette <mturquette@linaro.org>
      55b8fd4f