1. 15 11月, 2012 1 次提交
    • K
      ARM: OMAP4: PM: fix errata handling when CONFIG_PM=n · 93640735
      Kevin Hilman 提交于
      commit c9621844 (ARM: OMAP4: PM: add errata support) introduced errata
      handling for OMAP4, but was broken when CONFIG_PM=n.
      
      When CONFIG_PM=n, pm44xx.c is not compiled, yet that is where pm44xx_errata
      is defined.  However, these errata are needed for the SMP boot/hotplug case
      also, and are primarily used in omap-smp.c.
      
      Move the definition of pm44xx_errata to omap-smp.c so that it's available
      even in the CONFIG_PM=n case.
      
      Cc: Tero Kristo <t-kristo@ti.com>
      Signed-off-by: NKevin Hilman <khilman@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      93640735
  2. 07 11月, 2012 1 次提交
  3. 06 11月, 2012 3 次提交
    • C
      ARM: OMAP4: retrigger localtimers after re-enabling gic · cd8ce159
      Colin Cross 提交于
      'Workaround for ROM bug because of CA9 r2pX gic control'
      register change disables the gic distributor while the secondary
      cpu is being booted.  If a localtimer interrupt on the primary cpu
      occurs when the distributor is turned off, the interrupt is lost,
      and the localtimer never fires again.
      
      Make the primary cpu wait for the secondary cpu to reenable the
      gic distributor (with interrupts off for safety), and then
      check if the pending bit is set in the localtimer but not the
      gic.  If so, ack it in the localtimer, and reset the timer with
      the minimum timeout to trigger a new timer interrupt.
      Signed-off-by: NColin Cross <ccross@android.com>
      [s-jan@ti.com: adapted to k3.4 + validated functionality]
      Signed-off-by: NSebastien Jan <s-jan@ti.com>
      [t-kristo@ti.com: dropped generic ARM kernel exports from the code, rebased
       to mainline]
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Signed-off-by: NKevin Hilman <khilman@ti.com>
      cd8ce159
    • S
      ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change. · ff999b8a
      Santosh Shilimkar 提交于
      On OMAP4+ devices, GIC register context is lost when MPUSS hits
      the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
      gets executed and one of the steps in it is to restore the
      saved context of the GIC. The ROM Code GIC distributor restoration
      is split in two parts: CPU specific register done by each CPU and
      common register done by only one CPU.
      
      Below is the abstract flow.
      
      ...............................................................
      - MPUSS in OSWR state.
      - CPU0 wakes up on the event(interrupt) and start executing ROM code.
      
      [..]
      
      - CPU0 executes "GIC Restoration:"
      
      [...]
      
      - CPU0 swicthes to non-secure mode and jumps to OS resume code.
      
      [...]
      
      - CPU0 is online in OS
      - CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
      - CPU0 wakes up CPU1 with clock-domain force wakeup method.
      - CPU0 continues it's execution.
      [..]
      
      - CPU1 wakes up and start executing ROM code.
      
      [..]
      
      - CPU1 executes "GIC Restoration:"
      
      [..]
      
      - CPU1 swicthes to non-secure mode and jumps to OS resume code.
      
      [...]
      
      - CPU1 is online in OS and start executing.
      [...]   -
      
      GIC Restoration: /* Common routine for HS and GP devices */
      {
             if (GICD != 1)  { /* This will be true in OSWR state */
                     if (GIC_SAR_BACKUP_STATE == SAVED)
                             - CPU restores GIC distributor
                     else
                             - reconfigure GIC distributor to boot values.
      
                     GICD.Enable secure = 1
             }
      
             if (GIC_SAR_BACKUP_STATE == SAVED)
                     - CPU restore its GIC CPU interface registers if saved.
             else
                     - reconfigure its GIC CPU interface registers to boot
                             values.
      }
      ...............................................................
      
      So as mentioned in the flow, GICD != 1 condition decides how
      the GIC registers are handled in ROM code wakeup path from
      OSWR. As evident from the flow, ROM code relies on the entire
      GICD register value and not specific register bits.
      
      The assumption was valid till CortexA9 r1pX version since there
      was only one banked bit to control secure and non-secure GICD.
      Secure view which ROM code sees:
             bit 0 == Enable Non-secure
      Non-secure view which HLOS sees:
             bit 0 == Enable secure
      
      But GICD register has changed between CortexA9 r1pX and r2pX.
      On r2pX GICD register is composed of 2 bits.
      Secure view which ROM code sees:
             bit 1 == Enable Non-secure
             bit 0 == Enable secure
      Non-secure view which HLOS sees:
             bit 0 == Enable Non-secure
      
      Hence on OMAP4460(r2pX) devices, if you go through the
      above flow again during CPU1 wakeup, GICD == 3 and hence
      ROM code fails to understand the real wakeup power state
      and reconfigures GIC distributor to boot values. This is
      nasty since you loose the entire interrupt controller
      context in a live system.
      
      The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
      check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
      
      Since ROM code can't be fixed on OMAP4460 devices, a work around
      needs to be implemented. As evident from the flow, as long as
      CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
      won't happen. Below is the flow with the work-around.
      
      ...............................................................
      - MPUSS in OSWR state.
      - CPU0 wakes up on the event(interrupt) and start executing ROM code.
      
      [..]
      
      - CPU0 executes "GIC Restoration:"
      
      [..]
      
      - CPU0 swicthes to non-secure mode and jumps to OS resume code.
      
      [..]
      
      - CPU0 is online in OS.
      - CPU0 does GICD.Enable Non-secure = 0
      - CPU0 wakes up CPU1 with clock domain force wakeup method.
      - CPU0 waits for GICD.Enable Non-secure = 1
      - CPU0 coninues it's execution.
      [..]
      
      - CPU1 wakes up and start executing ROM code.
      
      [..]
      
      - CPU1 executes "GIC Restoration:"
      
      [..]
      
      - CPU1 swicthes to non-secure mode and jumps to OS resume code.
      
      [..]
      
      - CPU1 is online in OS
      - CPU1 does GICD.Enable Non-secure = 1
      - CPU1 start executing
      [...]
      ...............................................................
      
      With this procedure, the GIC configuration done between the
      CPU0 wakeup and CPU1 wakeup will not be lost but during this
      short windows, the CPU0 will not receive interrupts.
      
      The BUG is applicable to only OMAP4460(r2pX) devices.
      OMAP4470 (also r2pX) is not affected by this bug because
      ROM code has been fixed.
      Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Signed-off-by: NKevin Hilman <khilman@ti.com>
      ff999b8a
    • T
      ARM: OMAP4: PM: add errata support · c9621844
      Tero Kristo 提交于
      Added similar PM errata flag support as omap3 has. This should be used
      in similar manner, set the flags during init time, and check the flag
      values during runtime.
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Signed-off-by: NKevin Hilman <khilman@ti.com>
      c9621844
  4. 05 11月, 2012 1 次提交
  5. 04 11月, 2012 4 次提交
    • L
      Merge tag 'nfs-for-3.7-4' of git://git.linux-nfs.org/projects/trondmy/linux-nfs · d4164973
      Linus Torvalds 提交于
      Pull NFS client bugfixes from Trond Myklebust:
      
       - Fix a bunch of deadlock situations:
         * State recovery can deadlock if we fail to release sequence ids
           before scheduling the recovery thread.
         * Calling deactivate_super() from an RPC workqueue thread can
           deadlock because of the call to rpc_shutdown_client.
      
       - Display the device name correctly in /proc/*/mounts
      
       - Fix a number of incorrect error return values:
         * When NFSv3 mounts fail due to a timeout.
         * On NFSv4.1 backchannel setup failure
         * On NFSv4 open access checks
      
       - pnfs_find_alloc_layout() must check the layout pointer for NULL
      
       - Fix a regression in the legacy DNS resolved
      
      * tag 'nfs-for-3.7-4' of git://git.linux-nfs.org/projects/trondmy/linux-nfs:
        NFS4: nfs4_opendata_access should return errno
        NFSv4: Initialise the NFSv4.1 slot table highest_used_slotid correctly
        SUNRPC: return proper errno from backchannel_rqst
        NFS: add nfs_sb_deactive_async to avoid deadlock
        nfs: Show original device name verbatim in /proc/*/mount{s,info}
        nfsv3: Make v3 mounts fail with ETIMEDOUTs instead EIO on mountd timeouts
        nfs: Check whether a layout pointer is NULL before free it
        NFS: fix bug in legacy DNS resolver.
        NFSv4: nfs4_locku_done must release the sequence id
        NFSv4.1: We must release the sequence id when we fail to get a session slot
        NFS: Wait for session recovery to finish before returning
      d4164973
    • L
      Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux · 225ff868
      Linus Torvalds 提交于
      Pull thermal management & ACPI update from Zhang Rui,
      
      Ho humm.  Normally these things go through Len.  But it's just three
      small fixes, I guess I can pull directly too.
      
      * 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux:
        exynos4_tmu_driver_ids should be exynos_tmu_driver_ids.
        ACPI video: Ignore errors after _DOD evaluation.
        thermal: solve compilation errors in rcar_thermal
      225ff868
    • L
      Merge branch 'i2c-embedded/for-current' of git://git.pengutronix.de/git/wsa/linux · 209c510e
      Linus Torvalds 提交于
      Pull i2c embedded fixes from Wolfram Sang:
       "Two patches are usual stuff.
      
        The bigger patch is needed to correct a wrong decision made in this
        merge window.  We hoped to get the PIOQUEUE mode in the mxs driver
        working with DMA, but it turned out to be too broken (leading to data
        loss), so we now think it is best to remove it entirely and work only
        with DMA now.  The patch should be in 3.7.  IMO, so users never get
        the chance to use both modes in parallel."
      
      * 'i2c-embedded/for-current' of git://git.pengutronix.de/git/wsa/linux:
        i2c: tegra: set irq name as device name
        i2c-nomadik: Fixup clock handling
        i2c: mxs: remove broken PIOQUEUE support
      209c510e
    • L
      Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux · 53f9313f
      Linus Torvalds 提交于
      Pull drm fixes from Dave Airlie:
       "Scattered selection of fixes:
      
         - radeon: load detect fixes from SuSE/AMD
         - intel: misc i830, sdvo regression, vesafb kickoff ums fix
         - exynos: maintainers entry update + fixes
         - udl: fix stride scanout issue
      
        it's slightly bigger than I'd probably like, but nothing looked
        dangerous enough to hold off on."
      
      * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
        drm/udl: fix stride issues scanning out stride != width*bpp
        drm/radeon: add load detection support for ext DAC on R200 (v2)
        DRM/radeon: For single CRTC GPUs move handling of CRTC_CRT_ON to crtc_dpms().
        DRM/Radeon: Fix TV DAC Load Detection for single CRTC chips.
        DRM/Radeon: Clean up code in TV DAC load detection.
        drm/radeon: fix ATPX function documentation
        drivers/gpu/drm/radeon/evergreen_cs.c: Remove unnecessary semicolon
        DRM/Radeon: On DVI-I use Load Detection when EDID is bogus.
        DRM/Radeon: Fix primary DAC Load Detection for RV100 chips.
        DRM/Radeon: Fix Load Detection on legacy primary DAC.
        drm: exynos: removed warning due to missing typecast for mixer driver data
        drm/exynos: add support for ARCH_MULTIPLATFORM
        MAINTAINERS: Add git repository for Exynos DRM
        drm/exynos: fix display on issue
        drm/i915: Only kick out vesafb if we takeover the fbcon with KMS
        drm/i915: be less verbose about inability to provide vendor backlight
        drm/i915: clear the entire sdvo infoframe buffer
        drm/i915: VGA needs to be on pipe A on i830M
        drm/i915: fix overlay on i830M
      53f9313f
  6. 03 11月, 2012 21 次提交
  7. 02 11月, 2012 9 次提交