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  1. 29 6月, 2016 1 次提交
  3. 24 6月, 2016 3 次提交
  5. 23 6月, 2016 5 次提交
  7. 22 6月, 2016 3 次提交
    • I
      drm/i915: Group all the PPS init steps to one place · b4d06ede
      由 Imre Deak 提交于 
      Move the early PPS initialization calls next to the rest of PPS
initialization steps. This allows us to forgo a duplicated call to
intel_dp_init_panel_power_sequencer_registers() on VLV/CHV.

This will swap the order of DP AUX registration wrt. PPS initialization.
There is an existing race here in case of a user space access via the
DPAUX device node after DP AUX registration and before calling
intel_dp_init_panel_power_sequencer_registers(), but this change won't
make this worse. The fix for this is to separate DP AUX initialization
and registration, that's a separate work already underway.

The order of MST wrt. PPS init as well as the order of
intel_dp_init_panel_power_sequencer_registers() wrt.
intel_edp_panel_vdd_sanitize() also swap, which is ok, there are no
dependencies between these steps.

Suggested by Ville.

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466499109-20240-4-git-send-email-imre.deak@intel.com
      b4d06ede
    • I
      drm/i915: Initialize the PPS HW before its first use · 0080b5da
      由 Imre Deak 提交于 
      The initial DPCD read for eDP detection involves using the PPS, but so
far we only initialized the PPS registers after the DPCD read. The
reason this was done so far is to preserve a possible LVDS PPS HW setup
if LVDS is detected but eDP is not. This is not an issue any more after
the previous patch, so we can move the init earlier now.

This was caught by CI with the PPS sanity checks in place and the
initial eDP DPCD readout waiting for the panel power cycle timeout
without the PPS registers being initialized.

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466499109-20240-3-git-send-email-imre.deak@intel.com
      0080b5da
    • I
      drm/i915/ibx, cpt: Don't attempt to register eDP if LVDS was detected · 97a824e1
      由 Imre Deak 提交于 
      Atm on IBX/CPT we attempt to detect if eDP is present even if LVDS was
already detected and an encoder for it was registered. This involves
trying to read out the eDP DPCD, which in turn needs the same power
sequencer that LVDS uses. Poking at the VDD line at an unexpected time
may or may not interfere with the LVDS panel, but it's probably safer to
prevent this. Registering both an LVDS and an eDP connector would also
present a similar problem accessing the shared PPS at any point later in
an unexpected way.

We also need this to be able fix PPS initialization before its first use
in the next patch. For that we want to be sure that PPS is not in use
by LVDS.

v2:
- Split out the PPS init fix to a separate patch. (Chris)
- Add comment about eDP init depending on LVDS init. (Chris)
- Make the use of the intel_encoder ptr less error prone.
v3:
- Use IBX/CPT reference instead of the incorrect ILK, add a WARN about
  this. (Ville)
v4:
- Use a helper to get the lvds encoder instead of opencoding the same.
  (Ville)

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v3)
Link: http://patchwork.freedesktop.org/patch/msgid/1466499109-20240-2-git-send-email-imre.deak@intel.com
      97a824e1
  9. 20 6月, 2016 2 次提交
  11. 19 6月, 2016 1 次提交
  13. 11 6月, 2016 1 次提交
  15. 02 6月, 2016 2 次提交
  17. 01 6月, 2016 1 次提交
  19. 30 5月, 2016 1 次提交
  21. 24 5月, 2016 2 次提交
  23. 20 5月, 2016 1 次提交
  25. 29 4月, 2016 8 次提交
  27. 27 4月, 2016 1 次提交
  29. 26 4月, 2016 1 次提交
  31. 23 4月, 2016 1 次提交
  33. 19 4月, 2016 3 次提交
  35. 15 4月, 2016 1 次提交
  37. 13 4月, 2016 2 次提交