1. 10 9月, 2006 2 次提交
  2. 07 9月, 2006 1 次提交
  3. 03 9月, 2006 1 次提交
    • G
      [ARM] 3762/1: Fix ptrace cache coherency bug for ARM1136 VIPT nonaliasing Harvard caches · a188ad2b
      George G. Davis 提交于
      Patch from George G. Davis
      
      Resolve ARM1136 VIPT non-aliasing cache coherency issues observed when
      using ptrace to set breakpoints and cleanup copy_{to,from}_user_page()
      while we're here as requested by Russell King because "it's also far
      too heavy on non-v6 CPUs".
      
      NOTES:
      
      1. Only access_process_vm() calls copy_{to,from}_user_page().
      2. access_process_vm() calls get_user_pages() to pin down the "page".
      3. get_user_pages() calls flush_dcache_page(page) which ensures cache
         coherency between kernel and userspace mappings of "page".  However
         flush_dcache_page(page) may not invalidate I-Cache over this range
         for all cases, specifically, I-Cache is not invalidated for the VIPT
         non-aliasing case.  So memory is consistent between kernel and user
         space mappings of "page" but I-Cache may still be hot over this
         range.  IOW, we don't have to worry about flush_cache_page() before
         memcpy().
      4. Now, for the copy_to_user_page() case, after memcpy(), we must flush
         the caches so memory is consistent with kernel cache entries and
         invalidate the I-Cache if this mm region is executable.  We don't
         need to do anything after memcpy() for the copy_from_user_page()
         case since kernel cache entries will be invalidated via the same
         process above if we access "page" again.  The flush_ptrace_access()
         function (borrowed from SPARC64 implementation) is added to handle
         cache flushing after memcpy() for the copy_to_user_page() case.
      Signed-off-by: NGeorge G. Davis <gdavis@mvista.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      a188ad2b
  4. 31 8月, 2006 3 次提交
  5. 28 8月, 2006 2 次提交
  6. 27 8月, 2006 1 次提交
  7. 18 8月, 2006 2 次提交
  8. 02 8月, 2006 1 次提交
  9. 25 7月, 2006 1 次提交
    • M
      [ARM] 3731/1: Allow IRQ definitions of IQ80331 and IQ80332 to co-exist · d8ca3d11
      Martin Michlmayr 提交于
      Patch from Martin Michlmayr
      
      ARCH_IQ80331 and MACH_IQ80332 can be enabled at the same time but a
      header file makes certain IRQ definitions conditional, leading to
      the following compilation error when both platforms are enabled:
      
      arch/arm/mach-iop3xx/iq80332-pci.c: In function 'iq80332_map_irq':
      arch/arm/mach-iop3xx/iq80332-pci.c:54: error: 'IRQ_IQ80332_INTA' undeclared (first use in this function)
      arch/arm/mach-iop3xx/iq80332-pci.c:54: error: (Each undeclared identifier is reported only once
      arch/arm/mach-iop3xx/iq80332-pci.c:54: error: for each function it appears in.)
      arch/arm/mach-iop3xx/iq80332-pci.c:54: error: 'IRQ_IQ80332_INTB' undeclared (first use in this function)
      arch/arm/mach-iop3xx/iq80332-pci.c:54: error: 'IRQ_IQ80332_INTC' undeclared (first use in this function)
      arch/arm/mach-iop3xx/iq80332-pci.c:54: error: 'IRQ_IQ80332_INTD' undeclared (first use in this function)
      Signed-off-by: NMartin Michlmayr <tbm@cyrius.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      d8ca3d11
  10. 15 7月, 2006 1 次提交
    • S
      [PATCH] remove set_wmb - arch removal · 52393ccc
      Steven Rostedt 提交于
      set_wmb should not be used in the kernel because it just confuses the
      code more and has no benefit.  Since it is not currently used in the
      kernel this patch removes it so that new code does not include it.
      
      All archs define set_wmb(var, value) to do { var = value; wmb(); }
      while(0) except ia64 and sparc which use a mb() instead.  But this is
      still moot since it is not used anyway.
      
      Hasn't been tested on any archs but x86 and x86_64 (and only compiled
      tested)
      Signed-off-by: NSteven Rostedt <rostedt@goodmis.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      52393ccc
  11. 12 7月, 2006 1 次提交
    • R
      [ARM] Allow Versatile to be built for AB and PB · dc5bc8f1
      Russell King 提交于
      If a configuration was chosen to support both the Versatile
      AB and PB boards, the result would write to registers not
      available on the PB version of the board.  Resolve this by
      using machine_is_xxx().
      
      Also, for the CLCD, despite how the code looks, both the AB
      and PB access the same location to control the clock rate -
      it's just called something different between the two board
      versions.  Invent our own name for this location and use it
      unconditionally.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      dc5bc8f1
  12. 06 7月, 2006 1 次提交
  13. 03 7月, 2006 2 次提交
  14. 02 7月, 2006 3 次提交
  15. 01 7月, 2006 4 次提交
  16. 30 6月, 2006 3 次提交
    • C
      [AF_UNIX]: Datagram getpeersec · 877ce7c1
      Catherine Zhang 提交于
      This patch implements an API whereby an application can determine the
      label of its peer's Unix datagram sockets via the auxiliary data mechanism of
      recvmsg.
      
      Patch purpose:
      
      This patch enables a security-aware application to retrieve the
      security context of the peer of a Unix datagram socket.  The application
      can then use this security context to determine the security context for
      processing on behalf of the peer who sent the packet.
      
      Patch design and implementation:
      
      The design and implementation is very similar to the UDP case for INET
      sockets.  Basically we build upon the existing Unix domain socket API for
      retrieving user credentials.  Linux offers the API for obtaining user
      credentials via ancillary messages (i.e., out of band/control messages
      that are bundled together with a normal message).  To retrieve the security
      context, the application first indicates to the kernel such desire by
      setting the SO_PASSSEC option via getsockopt.  Then the application
      retrieves the security context using the auxiliary data mechanism.
      
      An example server application for Unix datagram socket should look like this:
      
      toggle = 1;
      toggle_len = sizeof(toggle);
      
      setsockopt(sockfd, SOL_SOCKET, SO_PASSSEC, &toggle, &toggle_len);
      recvmsg(sockfd, &msg_hdr, 0);
      if (msg_hdr.msg_controllen > sizeof(struct cmsghdr)) {
          cmsg_hdr = CMSG_FIRSTHDR(&msg_hdr);
          if (cmsg_hdr->cmsg_len <= CMSG_LEN(sizeof(scontext)) &&
              cmsg_hdr->cmsg_level == SOL_SOCKET &&
              cmsg_hdr->cmsg_type == SCM_SECURITY) {
              memcpy(&scontext, CMSG_DATA(cmsg_hdr), sizeof(scontext));
          }
      }
      
      sock_setsockopt is enhanced with a new socket option SOCK_PASSSEC to allow
      a server socket to receive security context of the peer.
      
      Testing:
      
      We have tested the patch by setting up Unix datagram client and server
      applications.  We verified that the server can retrieve the security context
      using the auxiliary data mechanism of recvmsg.
      Signed-off-by: NCatherine Zhang <cxzhang@watson.ibm.com>
      Acked-by: NAcked-by: James Morris <jmorris@namei.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      877ce7c1
    • R
      [ARM] Add section support to ioremap · ff0daca5
      Russell King 提交于
      Allow section mappings to be setup using ioremap() and torn down
      with iounmap().  This requires additional support in the MM
      context switch to ensure that mappings are properly synchronised
      when mapped in.
      
      Based an original implementation by Deepak Saxena, reworked and
      ARMv6 support added by rmk.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      ff0daca5
    • R
      [ARM] Set bit 4 on section mappings correctly depending on CPU · 8799ee9f
      Russell King 提交于
      On some CPUs, bit 4 of section mappings means "update the
      cache when written to".  On others, this bit is required to
      be one, and others it's required to be zero.  Finally, on
      ARMv6 and above, setting it turns on "no execute" and prevents
      speculative prefetches.
      
      With all these combinations, no one value fits all CPUs, so we
      have to pick a value depending on the CPU type, and the area
      we're mapping.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      8799ee9f
  17. 29 6月, 2006 11 次提交