提交 · 922783755b52097e671b3d0bae3363223aa5ae28 · openeuler / Kernel

16 7月, 2020 26 次提交

drm/amd/powerplay: drop unused code around thermal range setting · 3cd7e415

由 Evan Quan 提交于 7月 02, 2020

Leftover of previous cleanups.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

3cd7e415

drm/amd/powerplay: maximum the code sharing on thermal irq setting · 1e1964b7

由 Evan Quan 提交于 7月 02, 2020

Put the common code in smu_v11_0.c instead of having one copy each.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

1e1964b7

drm/amd/powerplay: sort the call flow on temperature ranges retrieving · 0540eced

由 Evan Quan 提交于 7月 02, 2020

This can help to maintain clear code layer.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

0540eced

drm/amd/powerplay: cache the software_shutdown_temp · e02e4d51

由 Evan Quan 提交于 7月 02, 2020

As it's needed in the succeeding thermal irq setting.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

e02e4d51

drm/amd/powerplay: correct Sienna Cichlid temperature limit settings · 2b1f12a2

由 Evan Quan 提交于 7月 02, 2020

These are needed for temp1/2/3 related hwmon interfaces.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

2b1f12a2

drm/amd/powerplay: correct Navi1X temperature limit settings · cbf3f132

由 Evan Quan 提交于 7月 02, 2020

These are needed for temp1/2/3 related hwmon interfaces.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

cbf3f132

drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCount · 0b590970

由 Evan Quan 提交于 7月 03, 2020

The LCLK dpm table setup should be performed in .update_pcie_parameters().
Otherwise, the updated GenSpeed and LaneCount information will be lost.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

0b590970

drm/amd/powerplay: drop unnecessary wrapper around pcie parameters setting · 778f8e6a

由 Evan Quan 提交于 7月 02, 2020

This can also help to maintain clear code layer.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

778f8e6a

drm/amd/powerplay: drop unused APIs and parameters · 42f75c84

由 Evan Quan 提交于 7月 02, 2020

Leftover of previous performance level setting cleanups.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

42f75c84

drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper V2 · 982d68b0

由 Evan Quan 提交于 7月 02, 2020

By moving the implemention to renoir_ppt.c considering
it's really ASIC specific.

V2: fix compile warnings below
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:40:25: warning: array subscript is above array bounds [-Warray-bounds]
    freq = table->FClocks[dpm_level].Freq; \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
  GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
  ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:46:25: warning: array subscript is above array bounds [-Warray-bounds]
    freq = table->FClocks[dpm_level].Freq;  \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
  GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

982d68b0

drm/amd/powerplay: drop unnecessary wrappers · d56ff011

由 Evan Quan 提交于 7月 02, 2020

By calling the target APIs directly.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

d56ff011

drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs · 5a7092ae

由 Evan Quan 提交于 7月 10, 2020

Before and after setting gfx clock soft max/min frequency.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

5a7092ae

drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range · 10e96d89

由 Evan Quan 提交于 7月 02, 2020

Use the common smu_v11_0_set_soft_freq_limited_range.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

10e96d89

drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIs · b2785e25

由 Evan Quan 提交于 7月 02, 2020

As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

b2785e25

drm/amd/powerplay: drop unnecessary Navi1x specific APIs · 46a301e1

由 Evan Quan 提交于 7月 02, 2020

As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

46a301e1

drm/amd/powerplay: drop unnecessary Arcturus specific APIs · 5a52694c

由 Evan Quan 提交于 7月 02, 2020

As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

5a52694c

drm/amd/powerplay: update the common API for performance level setting · 768bb901

由 Evan Quan 提交于 7月 02, 2020

So that it can be more widely shared around SMU v11 ASICs.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

768bb901

drm/amd/powerplay: update UMD pstate clock settings · 62cc9dd1

由 Evan Quan 提交于 6月 10, 2020

Preparing for coming code sharing around performance level
setting.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

62cc9dd1

drm/amd/powerplay: add new UMD pstate data structure · b64d8688

由 Evan Quan 提交于 6月 10, 2020

This is used to cache the clock frequencies for all UMD pstates.
So that we do not need to calculate from scratch on every UMD
pstate switch.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

b64d8688

drm/amd/powerplay: update Sienna Cichlid default dpm table setup · 90a89c31

由 Evan Quan 提交于 6月 10, 2020

Cache all clocks levels for every dpm table. They are needed
by other APIs.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

90a89c31

drm/amd/powerplay: update Navi10 default dpm table setup · 3afb244b

由 Evan Quan 提交于 6月 10, 2020

Cache all clocks levels for every dpm table. They are needed
by other APIs.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

3afb244b

drm/amd/powerplay: update Arcturus default dpm table setting · 3a86d7f6

由 Evan Quan 提交于 7月 10, 2020

Preparing for coming code sharing around performance level
setting.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

3a86d7f6

drm/amd/powerplay: implement a common set dpm table API for smu V11 · c1a9e61c

由 Evan Quan 提交于 7月 10, 2020

Maximum the code sharing around smu V11.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

c1a9e61c

drm/amd/powerplay: add more members for dpm table · 4387b104

由 Evan Quan 提交于 6月 10, 2020

These members can help to cache the clock frequencies for all
dpm levels. Then simplifying the code for dpm level switching
is possible.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

4387b104

drm/amdgpu: enable mode1 reset · 311531f0

由 Wenhui Sheng 提交于 7月 13, 2020

For sienna cichlid, add mode1 reset path for sGPU.

v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1
v3: split emergency restart logic to a new patch
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Signed-off-by: NWenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

311531f0

drm/amd/powerplay: add SMU mode1 reset · ea8139d8

由 Wenhui Sheng 提交于 7月 10, 2020

From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset
is support, driver sends PPSMC_MSG_Mode1Reset message
to PM FW could trigger this reset.

v2: add mode1 reset dpm interface
v3: change maro name
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Signed-off-by: NWenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

ea8139d8

15 7月, 2020 2 次提交

drm/amdgpu/powerplay: Modify SMC message name for setting power profile mode · 3a4024b5

由 chen gong 提交于 7月 13, 2020

I consulted Cai Land(Chuntian.Cai@amd.com), he told me corresponding smc
message name to fSMC_MSG_SetWorkloadMask() is
"PPSMC_MSG_ActiveProcessNotify" in firmware code of Renoir.

Strange though it may seem, but it's a fact.
Signed-off-by: Nchen gong <curry.gong@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

3a4024b5

drm/amdgpu/powerplay: Target power profile mode should be the second parameter... · 4c8f126e

由 chen gong 提交于 7月 10, 2020

drm/amdgpu/powerplay: Target power profile mode should be the second parameter of renoir_set_power_profile_mode

A small mistake
Signed-off-by: Nchen gong <curry.gong@amd.com>
Acked-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

4c8f126e

11 7月, 2020 10 次提交

drm/amd/powerplay: put dpm frequency setting common code in smu_v11_0.c · d8d3493a

由 Evan Quan 提交于 6月 09, 2020

As designed the common code shared among all smu v11 ASCIs go to
smu_v11_0.c. This helps to maintain clear code layers.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

d8d3493a

drm/amd/powerplay: revise calling chain on retrieving frequency range · e5ef784b

由 Evan Quan 提交于 6月 09, 2020

This helps to maintain clear code layers and drop unnecessary
parameter.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

e5ef784b

drm/amd/powerplay: revise calling chain on setting soft limit · c98f31d1

由 Evan Quan 提交于 6月 09, 2020

This helps to maintain clear code layers and drop unnecessary
parameter.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

c98f31d1

drm/amd/powerplay: put setting hard limit common code in smu_v11_0.c · 661b94f5

由 Evan Quan 提交于 6月 09, 2020

As designed the common code shared among all smu v11 ASCIs go to
smu_v11_0.c. This helps to maintain clear code layers.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

661b94f5

drm/amd/powerplay: drop unused code and wrapper around clock retrieving · b2febc99

由 Evan Quan 提交于 6月 09, 2020

Clean code by dropping unnecessary ones.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

b2febc99

drm/amd/powerplay: unshare the code for retrieving current clock frequency · e0f9e936

由 Evan Quan 提交于 6月 09, 2020

By moving them into asic specific file. Since they are really ASIC
specific.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

e0f9e936

drm/amd/powerplay: bypass wrapper on retrieving current clock frequency · 5e6dc8fe

由 Evan Quan 提交于 6月 09, 2020

By calling the target API(asic specific) directly.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

5e6dc8fe

drm/amd/powerplay: drop unnecessary wrappers around clock retrieving · 9b259eae

由 Evan Quan 提交于 6月 09, 2020

By calling the target APIs directly.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

9b259eae

drm/amd/powerplay: update driver if file for sienna_cichlid · ec114eb4

由 Likun Gao 提交于 7月 09, 2020

Update sienna_cichlid driver if header and related files.
Signed-off-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

ec114eb4

drm/amd/powerplay: correct the .get_workload_type() pointer · f21128fd

由 Evan Quan 提交于 7月 03, 2020

This seemed a typo.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

f21128fd

03 7月, 2020 2 次提交

drm/amd/powerplay: fix compile error with ARCH=arc · 9822ba2e

由 Evan Quan 提交于 6月 28, 2020

Fix the compile error below:
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function 'smu_v11_0_init_microcode':
>> arch/arc/include/asm/bug.h:22:2: error: implicit declaration of function 'pr_warn'; did you mean 'pci_warn'? [-Werror=implicit-function-declaration]
      22 |  pr_warn("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
         |  ^~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:176:3: note: in expansion of macro 'BUG'
     176 |   BUG();
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

9822ba2e

drm/amd/powerplay: drop unnecessary "@" on OD sysfs output · d818ed28

由 Evan Quan 提交于 6月 17, 2020

To follow conventional style. And this unnecessary "@" confuses
our userspace tool.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

d818ed28

openeuler / Kernel 接近 2 年 前同步成功

openeuler / Kernel
接近 2 年前同步成功