1. 11 5月, 2011 17 次提交
  2. 31 3月, 2011 1 次提交
  3. 23 3月, 2011 1 次提交
  4. 18 3月, 2011 2 次提交
    • M
      OMAP: DSS2: Implement OMAP4 DSS fclk support · 2de11086
      Murthy, Raghuveer 提交于
      Add dss.dpll4_m4_ck (DSS FCLK) initialization for OMAP4. This is used
      to compute the pixel clock for DPI interface and also to reconfigure
      the DSS FCLK to the desired rate, corresponding to the rate computed
      for pixel clock.
      
      Adding these cpu_is_44xx() checks are meant to be temporary, until a
      cleaner implementation to manage these checks are added. Currently this
      is needed to get DVI display running on OMAP4 PandaBoard
      Signed-off-by: NRaghuveer Murthy <raghuveer.murthy@ti.com>
      [tomi.valkeinen@ti.com: minor changes due to conflicts]
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      2de11086
    • T
      OMAP: DSS2: Clean up for dpll4_m4_ck handling · 0acf659f
      Tomi Valkeinen 提交于
      OMAP2 does not have dpll4_m4_ck source clock for dss functional clock,
      but later OMAPs do. Currently we check for cpu type in multiple places
      to find out if dpll4_m4_ck is available.
      
      This patch cleans up dss.c by using the fact that dss.dpll4_m4_ck
      pointer is NULL on OMAP2. This allows us to remove many of the cpu
      checks.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      0acf659f
  5. 16 3月, 2011 8 次提交
  6. 15 3月, 2011 9 次提交
  7. 14 3月, 2011 1 次提交
  8. 11 3月, 2011 1 次提交
    • T
      OMAP4: DSS2: Clock source changes for OMAP4 · ea75159e
      Taneja, Archit 提交于
      On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as:
      
      Lcd Pixel clock = DISPC_FCLK / lcd / pcd
      
      Where lcd and pcd are divisors in the DISPC_DIVISOR register.
      
      On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new
      clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as:
      
      Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2
      
      Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers.
      
      LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL
      and DSI2 PLL as clock sources respectively. Introduce functions to select and
      get the clock source for these new clocks. Modify DISPC functions get the
      correct lck and pck rates based on the clock source of these clocks. Since
      OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source
      as DSS_CLK_SRC_FCK by introducing a dss feature.
      
      Introduce clock source names for OMAP4 and some register field changes in
      DSS_CTRL on OMAP4.
      
      Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL
      functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as
      clock.
      Signed-off-by: NArchit Taneja <archit@ti.com>
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      ea75159e