Adds a driver for the Si5341 and Si5340 chips. The driver does not fully
support all features of these chips, but allows the chip to be used
without any support from the "clockbuilder pro" software.

If the chip is preprogrammed, that is, you bought one with some defaults
burned in, or you programmed the NVM in some way, the driver will just
take over the current settings and only change them on demand. Otherwise
the input must be a fixed XTAL in its most basic configuration (no
predividers, no feedback, etc.).

The driver supports dynamic changes of multisynth, output dividers and
enabling or powering down outputs and multisynths.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
[sboyd@kernel.org: Mark some things static, use BIT_ULL for big bits and
ULL for big constants]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

RK809 and RK817 are power management IC chips for multimedia products.
most of their functions and registers are same, including the clkout
funciton.
Signed-off-by: NTony Xie <tony.xie@rock-chips.com>
Acked-by: NStephen Boyd <sboyd@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

ROHM BD70528 is an ultra low power PMIC with similar 32K clk as
bd718x7. Only difference (from clk perspective) is register address.
Add support for controlling BD70528 clk using bd718x7 driver.
Signed-off-by: NMatti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-by: NStephen Boyd <sboyd@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Building COMMON_CLK_XGENE is pointless, unless we're building for
an XGENE system.
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add driver code for the SiFive FU540 PRCI IP block.  This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra <wesley@sifive.com>:
https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

This version includes several changes requested by Stephen Boyd
<sboyd@kernel.org>.
Signed-off-by: NPaul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Wesley W. Terpstra <wesley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Megan Wachs <megan@sifive.com>
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-clk@vger.kernel.org
[sboyd@kernel.org: Fix some const and ARRAY_SIZE() issues, make makefile
only descend if CLK_SIFIVE=y]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add common library code for the Analog Bits Wide-Range PLL (WRPLL) IP
block, as implemented in TSMC CLN28HPC.

There is no bus interface or register target associated with this PLL.
This library is intended to be used by drivers for IP blocks that
expose registers connected to the PLL configuration and status
signals.

Based on code originally written by Wesley Terpstra
<wesley@sifive.com>:
https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60

This version incorporates several changes requested by Stephen
Boyd <sboyd@kernel.org>.
Signed-off-by: NPaul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Wesley Terpstra <wesley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Megan Wachs <megan@sifive.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
[sboyd@kernel.org: Fix some const issues]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Lochnagar is an evaluation and development board for Cirrus
Logic Smart CODEC and Amp devices. It allows the connection of
most Cirrus Logic devices on mini-cards, as well as allowing
connection of various application processor systems to provide a
full evaluation platform. This driver supports the board
controller chip on the Lochnagar board.

The Lochnagar can take several input clocks from the host system,
provides several of its own clock sources, and provides extensive
routing options for those clocks to be supplied to the attached
CODEC/Amp device.
Signed-off-by: NCharles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

We used to have a clock framework that isn't really used these days, except
for a few clocks and/or SoCs. Most of the time, the new framework and
drivers (sunxi-ng) will provide everything needed for the customer devices
to operate properly.

Since we're not needing it that much, it might make sense to disable those
drivers, for example when we want to reduce the kernel size. Let's add
options in Kconfig that can be disabled if needed, but are still on by
default to keep the same features in the standard case.
Acked-by: NStephen Boyd <sboyd@kernel.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>

This patch adds a driver for Fixed MMIO clock.
The driver reads a clock frequency value from a single 32-bit memory
mapped register and registers it as a fixed rate clock.

It can be enabled with COMMON_CLK_FIXED_MMIO Kconfig option.
Signed-off-by: NJan Kotas <jank@cadence.com>
[sboyd@kernel.org: Make of_fixed_mmio_clk_setup() static, use clk_hw
based APIs]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Commit d360b130 ("clk: imx: Make the i.MX8MQ CCM clock driver
CLK_IMX8MQ dependant") introduced this duplicate and incorrectly ordered
kconfig include.

Fixes: d360b130 ("clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant")
Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
Reviewed-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Remove the dependency between the i.MX8MQ CCM clock driver
and the CONFIG_SOC_IMX8MQ and use CONFIG_CLK_IMX8MQ instead.
CONFIG_CLK_IMX8MQ depends on ARCH_MXC && ARM64.
Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The patch introduces CONFIG_MXC_CLK option for legacy MMIO clocks,
this is required to compile legacy MMIO clock conditionally when adding
SCU based clocks for MX8 platforms later.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

ROHM bd71837 and bd71847 contain 32768Hz clock gate. Support the clock
using generic clock framework. Note, only bd71837 is tested but bd71847
should be identical what comes to clk parts.
Signed-off-by: NMatti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Previously, the CGU code corresponding to the SoC for which we're
compiling the kernel was the only one enabled, which made it impossible
to build one kernel that supports them all.

Now, it is possible to select more than one SoC to support.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This patch adds CCF compliant clock driver for ZynqMP.
Clock driver queries supported clock information from
firmware and regiters pll and output clocks with CCF.
Signed-off-by: NRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: NTejas Patel <tejasp@xilinx.com>
Signed-off-by: NShubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: NJolly Shah <jolly.shah@xilinx.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Reviewed-by: NStephen Boyd <sboyd@kernel.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch adds a driver for MAX9485, a programmable audio clock generator.

The device requires a 27.000 MHz clock input. It can provide a gated
buffered output of its input clock and two gated outputs of a PLL that can
generate one out of 16 discrete frequencies. There is only one PLL however,
so the two gated outputs will always have the same frequency but they can
be switched individually.

The driver for this device exposes 4 clocks in total:

- MAX9485_MCLKOUT:      A gated, buffered output of the input clock
- MAX9485_CLKOUT:       A PLL that can be configured to 16 different
			discrete frequencies
- MAX9485_CLKOUT[1,2]:  Two gated outputs for MAX9485_CLKOUT

Some PLL output frequencies can be achieved with different register
settings. The driver will select the one with lowest jitter in such cases.
Signed-off-by: NDaniel Mack <daniel@zonque.org>
[sboyd@kernel.org: Use local variable for val in max9485_clkout_recalc_rate()
and shorten line of max9485_of_clk_get()]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Clock driver is mandatory if the machine is selected.
Then don't use 'bool' and 'depends on' commands, but 'def_bool'
with the machine(s).

Fixes: da32d353 ("clk: stm32: add configuration flags for each of the stm32 drivers")
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for Actions Semi common clock driver with generic structures
and interface functions.
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This patch adds the driver and devicetree documentation for the
Silicon Labs SI544 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 200kHz
to 1500MHz.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
[sboyd: assign max_freq to 0 in is_valid_frequency() to squelch warning]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Without COMMON_CLK_HI655X Wifi and bluetooth are non-functional on Hikey.
As suggested by Arnd, enable the driver automatically when the parent
driver is selected. With sensible defaults in place, we can leave other
choices for EXPERT.

Cc: John Stultz <john.stultz@linaro.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Suggested-by: NArnd Bergmann <arnd@linaro.org>
Signed-off-by: NRiku Voipio <riku.voipio@linaro.org>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add two configuration flags to be able to not compile all the time
stm32f and stm32h7 drivers when ARCH_STM32 is set.
That help to save some space on those small platforms.
Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This patch introduces the mechanism to probe stm32mp1 driver.
It also defines registers definition.
This patch also introduces the generic mechanism to register
a clock (a simple gate, divider and fixed factor).

All clocks will be defined in one table.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Management Interface(SCMI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.

This patch adds support for the clocks provided by SCP using SCMI
protocol.

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

This adds the stub of a driver for the ASPEED SoCs. The clocks are
defined and the static registration is set up.
Reviewed-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Added Spreadtrum's clock driver framework together with common
structures and interface functions.
Signed-off-by: NChunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The RK808 and RK805 PMICs are using a similar register map.
We can reuse the clk driver for the RK805 PMIC. So let's add
the RK805 in the Kconfig description.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NJoseph Chen <chenjh@rock-chips.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

HSDK board manages its clocks using various PLLs. These PLL have same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.

Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the
HSDK arc cpus, system, ddr, AXI tunnel and hdmi.

By this patch we add support for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: NVineet Gupta <vgupta@synopsys.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901.
This chip has two clock inputs (external XTAL or external CLKIN), four
fractional dividers (FODs) and five clock outputs (four universal clock
outputs and one reference clock output at OUT0_SELB_I2C).
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Tested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
on Salvator-XS with the display LVDS output.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a driver for the clocks provided by the MIPS Boston board from
Imagination Technologies. 2 clocks are provided - the system clock & the
CPU clock - and each is a simple fixed rate clock whose frequency can be
determined by reading a register provided by the board.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16483/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock
controller that derive all clocks from a single crystal, using some
documented and some undocumented PLLs, half dividers, counters and
gates. This is a best attempt to construct a clock driver for the
clocks so at least we can gate off unused hardware and driver the
PCI bus clock.
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
[sboyd@codeaurora.org: Fix devm_ioremap_resource() return value
checking]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

In K2G, the clock handling is done through firmware executing on a
separate core. Linux kernel needs to communicate to the firmware
through TI system control interface to access any power management
related resources, including clocks.

The keystone sci-clk driver does this, by communicating to the
firmware through the TI SCI driver. The driver adds support for
registering clocks through DT, and basic required clock operations
like prepare/get_rate, etc.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Make ti_sci_init_clocks() static]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The hi655x multi function device is a PMIC providing regulators.

The PMIC also provides a clock for the WiFi and the Bluetooth, let's implement
this clock in order to add it in the hi655x MFD and allow proper wireless
initialization.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
[sboyd@codeaurora.org: Remove clkdev usage]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These
chips have two clock inputs, XTAL or CLK, which are muxed into single
PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip
while the 5P49V5923 requires external XTAL.

The PLL feeds two fractional dividers. Each fractional divider feeds
output mux, which allows selecting between clock from the fractional
divider itself or from output mux on output N-1. In case of output
mux 0, the output N-1 is instead connected to the output from the mux
feeding the PLL.

The driver thus far supports only the 5P49V5923 and 5P49V5933, while
it should be easily extensible to the whole 5P49V59xx family of chips
as they are all pretty similar.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The CDCE925 is a member of the CDCE(L)9xx programmable clock generator
family.  There are also CDCE913, CDCE937, CDCE949 which have different
number of PLLs and outputs.

The clk-cdce925 driver supports only CDCE925 in the family.  This adds
support for the CDCE913, CDCE937, CDCE949, too.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Cc: Michael Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

s2mps11 and max77686 clock drivers can be compile tested to increase
build coverage.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This includes UniPhier clock driver code, except SoC-specific
data arrays.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.
Signed-off-by: NShunli Wang <shunli.wang@mediatek.com>
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NErin Lo <erin.lo@mediatek.com>
Tested-by: NJohn Crispin <blogic@openwrt.org>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Maxim Max77620 has one 32KHz clock output and the clock HW
IP used on this PMIC is same as what it is there in the MAX77686.

Add clock driver support for MAX77620 on the MAX77686 driver.

CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clock IP used on the Maxim PMICs max77686 and max77802 are
same. The configuration of clock register is also same except
the number of clocks.

Part of common code utilisation, there is 3 files for these chips
clock driver, one for common and two files for driver registration.

Combine both drivers into single file and move common code into
same common file reduces the 2 files and make max77686 and max77802
clock driver in single fine. This driver does not depends on the
parent driver structure. The regmap handle is acquired through
regmap APIs for the register access.

This combination of driver helps on adding clock driver for different
Maxim PMICs which has similar clock IP like MAX77620 and MAX20024.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clk-oxnas driver is specific to its architecture, so do not
propose it on other architectures, unless build-testing.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160707091844.196a7930@endymion