- 01 7月, 2020 3 次提交
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由 Boyuan Zhang 提交于
Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0 These two macros are used specifically for VCN1.0, therefore rename it from general name to VCN1.0 specific name. Signed-off-by: NBoyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: NJames Zhu <james.zhu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Boyuan Zhang 提交于
Add range for vcn instance 1 for translation for internal register offset, which is needed for VCN3.0 V2: update description. Signed-off-by: NBoyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: NJames Zhu <james.zhu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
With basic IP block functions and ring functions Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NJames Zhu <James.Zhu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 4月, 2020 2 次提交
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由 James Zhu 提交于
VCN shared memory needs restore after wake up during S3 test. v2: Allocate shared memory saved_bo at sw_init and free it in sw_fini. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nirmoy Das 提交于
Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: NNirmoy Das <nirmoy.das@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 4月, 2020 3 次提交
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由 James Zhu 提交于
Added firmware share memory support for VCN. Current multiple queue mode is enabled only. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
Couldn't only rely on enc fence to decide switching to dpg unpaude mode. Since a enc thread may not schedule a fence in time during multiple threads running situation. v3: 1. Rename enc_submission_cnt to dpg_enc_submission_cnt 2. Add dpg_enc_submission_cnt check in idle_work_handler v4: Remove extra counter check, and reduce counter before idle work schedule Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> -
由 James Zhu 提交于
Fix race condition issue when multiple vcn starts are called. v2: Removed checking the return value of cancel_delayed_work_sync() to prevent possible races here. v3: Add total_submission_cnt to avoid gate power unexpectedly. v4: Remove extra counter check, and reduce counter before idle work schedule Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 12 2月, 2020 1 次提交
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由 James Zhu 提交于
Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode power off issue on instance 1. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 08 2月, 2020 1 次提交
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由 James Zhu 提交于
Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode power off issue on instance 1. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 28 1月, 2020 2 次提交
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由 James Zhu 提交于
Use inst_idx relacing inst in SOC15_DPG_MODE macro to avoid confusion. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
Fix typo error, should be inst_idx instead of inst. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 17 1月, 2020 3 次提交
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由 James Zhu 提交于
Move macro from vcn2.0 to amdgpu_vcn to share with vcn2.5 v2: squash in macro fix Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
Add multiple instance direct SRAM read and write support for vcn2.5 v2: squash in indexing fix Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
Add multiple-instance dpg pause mode support for VCN2.5 Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 12月, 2019 2 次提交
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由 Nirmoy Das 提交于
This sched array can be passed on to entity creation routine instead of manually creating such sched array on every context creation. v2: squash in missing break fix Signed-off-by: NNirmoy Das <nirmoy.das@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
Because VCN1.0 power management and DPG mode are managed together with JPEG1.0 under both HW and FW, so separated them from general VCN code. Also the multiple instances case got removed, since VCN1.0 HW just have a single instance. v2: override work func with vcn1.0's own Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 11月, 2019 1 次提交
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由 Leo Liu 提交于
And clean up the duplicated stuff Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 8月, 2019 1 次提交
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由 Thong Thai 提交于
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: NThong Thai <thong.thai@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 7月, 2019 1 次提交
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由 Thong Thai 提交于
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: NThong Thai <thong.thai@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 7月, 2019 3 次提交
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由 James Zhu 提交于
Add VCN harvest support for Arcturus Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
Arcturus has dual-VCN. Need Restruct amdgpu_device::vcn to support multiple vcns. There are no any logical changes here Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
So the ring functions can be shared with different VCN versions with different internal registers offsets Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 6月, 2019 8 次提交
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由 Leo Liu 提交于
SRAM will be programmed by PSP Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NJames Zhu <James.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
This will be used later for indirect SRAM mode Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NJames Zhu <James.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
This will be the basic and used for DPG mode Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NJames Zhu <James.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
No UVDW tile any more from VCN2.0, so mark out related fields. It fixes error: "[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa" Signed-off-by: NLeo Liu <leo.liu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
VCN (Video Core Next) is the video encode/decode block. Porting over the same functions from VCN1.0 v2: squash in updates (Alex) Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NJames Zhu <James.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
Use register from JPEG tile, the UVD tile reg won't work for JPEG Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
Add internal register offset for registers involving in ib tests Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
Add internal register offset for registers involving in ring tests Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 25 5月, 2019 2 次提交
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由 Leo Liu 提交于
It should be attached to VCN 1.0 Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Liu 提交于
Since this is VCN specific and only used by VCN Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 10 10月, 2018 1 次提交
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由 James Zhu 提交于
Correct VCN cache window definition. The old one is reused from UVD, and it is not fully correct. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Acked-by: NLeo Liu <leo.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 27 9月, 2018 2 次提交
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由 James Zhu 提交于
Add DPG pause state to support VCN DPG mode. Signed-off-by: NJames Zhu <James.Zhu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHuang Rui <ray.huang@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 James Zhu 提交于
When VCN PG state is unchanged, it is unnecessary to reset power gate state Signed-off-by: NJames Zhu <James.Zhu@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 16 6月, 2018 3 次提交
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由 Boyuan Zhang 提交于
Add an ib test for vcn jpeg. Signed-off-by: NBoyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Boyuan Zhang 提交于
Add a ring test for vcn jpeg. Signed-off-by: NBoyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Boyuan Zhang 提交于
Add jpeg to amdgpu_vcn v2: remove unnecessary scheduler entity Signed-off-by: NBoyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 5月, 2018 1 次提交
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由 Leo Liu 提交于
It should be stateless, and no need for scheduler to take care specially. Signed-off-by: NLeo Liu <leo.liu@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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