- 21 12月, 2018 1 次提交
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由 Evan Quan 提交于
Support manual LCLK DPM level switch on Vega20. Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NRex Zhu <Rex.Zhu@amd.com> Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 13 12月, 2018 1 次提交
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由 Evan Quan 提交于
Since this is not needed any more on the latest SMC firmware. Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NFeifei Xu <Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 11 12月, 2018 2 次提交
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由 Alex Deucher 提交于
Add special avfs handling for some polaris variants. v2: fix copy paste typo. v3: fix asic rid check Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Kenneth Feng 提交于
Instead of EVV cks-off voltages, avfs cks-off voltages can avoid the overshoot voltages when switching sclk. Signed-off-by: NKenneth Feng <kenneth.feng@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 08 12月, 2018 4 次提交
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由 hersen wu 提交于
[WHY] clarify dal input parameters to pplib interface, remove un-used parameters. dal knows exactly which parameters needed and their effects at pplib and smu sides. current dal sequence for dcn1_update_clock to pplib: 1.smu10_display_clock_voltage_request for dcefclk 2.smu10_display_clock_voltage_request for fclk 3.phm_store_dal_configuration_data { set_min_deep_sleep_dcfclk set_active_display_count store_cc6_data --- this data never be referenced new sequence will be: 1. set_display_count --- need add new pplib interface 2. set_min_deep_sleep_dcfclk -- new pplib interface 3. set_hard_min_dcfclk_by_freq 4. set_hard_min_fclk_by_freq after this code refactor, smu10_display_clock_voltage_request, phm_store_dal_configuration_data will not be needed for rv. [HOW] step 1: add new functions at pplib interface step 2: add new functions at amdgpu dm and dc Signed-off-by: Nhersen wu <hersenxs.wu@amd.com> Reviewed-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Check if the MC firmware supports FFC and tell the SMC so mclk switching is handled properly. Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Add new messages for polaris. Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Some new variants require updated firmware. V2: add MODULE_FIRMWARE for new firmwares Reviewed-by: Huang Rui <ray.huang@amd.com> (v1) Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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- 06 12月, 2018 2 次提交
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由 Alex Deucher 提交于
Adjust limits for newer polaris variants. v2: fix polaris11 kicker (Jerry) Reviewed-by: NJunwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Update switch limit on newer polaris variants. This may fix flickering with high refresh rates with mclk switching enabled. Reviewed-by: NJunwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 05 12月, 2018 1 次提交
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由 tianci yin 提交于
add protection code to avoid lower frequency trigger over drive. Reviewed-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NTianci Yin <tianci.yin@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 04 12月, 2018 3 次提交
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由 Evan Quan 提交于
For some case, no need to force SoftMin/Max settings for all DPMs. It's OK to force on some specific DPM only. Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
For display config change event only, pre-display config settings are needed. Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
New pptable upload through sysfs interface is supported. Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 29 11月, 2018 1 次提交
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由 Colin Ian King 提交于
There are spelling mistakes in PP_ASSERT_WITH_CODE messages, fix these. Signed-off-by: NColin Ian King <colin.king@canonical.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 27 11月, 2018 2 次提交
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由 Guttula, Suresh 提交于
Add hwmgr callback "update_nbdpm_pstate".This will use to access "cz_nbdpm_pstate_enable_disable" function to enable/disable low memory pstate. Signed-off-by: Nsuresh guttula <suresh.guttula@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Shirish S 提交于
This reverts commit dbd8299c32f6f413f6cfe322fe0308f3cfc577e8. Reason for revert: This patch sends msg PPSMC_MSG_DisableLowMemoryPstate(0x002e) in wrong of sequence to SMU which is before PPSMC_MSG_UVDPowerON (0x0008). This leads to SMU failing to service the request as it is dependent on UVD to be powered ON, since it accesses UVD registers. This msg should ideally be sent only when the UVD is about to decode a 4k video. Signed-off-by: NShirish S <shirish.s@amd.com> Signed-off-by: Nsuresh guttula <suresh.guttula@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 20 11月, 2018 3 次提交
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由 Greathouse, Joseph 提交于
Reading the sysfs files pp_sclk_od and pp_mclk_od return the percentage difference between the VBIOS-provided default frequency and the current (possibly user-set) frequency in the highest SCLK and MCLK DPM states, respectively. Writing to these files provides an easy mechanism for setting a higher-than-default maximum frequency. We normally only allow values >= 0 to be written here. However, with the addition of pp_od_clk_voltage, we now allow users to set custom DPM tables. If they then set the maximum DPM state to something less than the default, later reads of pp_*_od should return a negative value. The highest DPM state is now less than the VBIOS-provided default, so the percentage is negative. The math to calculate this was originally performed with unsigned values, meaning reads that should return negative values returned meaningless data. This patch corrects that issue and normalizes how all of the calculations are done across the various hwmgr types. Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NJoseph Greathouse <Joseph.Greathouse@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Disable these features on Vega20 for now. Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: Feifei Xu<Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Joerg Roedel 提交于
Running kfdtest on an AMD Carizzo flooded the kernel log with thousands of these "was not implemented" messages, making it impossible to see other messages there. Ratelimit the messages to prevent user-space from flooding the kernel log. Signed-off-by: NJoerg Roedel <jroedel@suse.de> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 13 11月, 2018 3 次提交
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由 Rex Zhu 提交于
the clk value should be tranferred to MHz first and then transfer to uint16. otherwise, the clock value will be truncated. Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reported-by: NHersen Wu <hersenxs.wu@amd.com> Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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由 Shirish S 提交于
This patch prints the version of SMU firmware. Signed-off-by: NShirish S <shirish.s@amd.com> Reviewed-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Daniel Kurtz 提交于
This patch refactors smu8_send_msg_to_smc_with_parameter() to include smu8_send_msg_to_smc_async() so that all the messages sent to SMU can be profiled and appropriately reported if they fail. Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NShirish S <shirish.s@amd.com> Reviewed-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 10 11月, 2018 1 次提交
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由 Likun Gao 提交于
Abstract the function of amdgpu_gfx_rlc_enter/exit_safe_mode and some part of rlc_init to improve the reusability of RLC. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 11月, 2018 1 次提交
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由 Jim Qu 提交于
Whitespace cleanup. Signed-off-by: NJim Qu <Jim.Qu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 08 11月, 2018 4 次提交
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由 Evan Quan 提交于
With UCLK DPM enabled, slow switching is not supported any more. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Otherwise big gap between these two clocks may causes some hangs. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
With UCLK DPM enabled, slow switching is not supported any more. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Otherwise big gap between these two clocks may causes some hangs. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 06 11月, 2018 3 次提交
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由 Evan Quan 提交于
Convert the operands on the two sides into the same granularity. Signed-off-by: NEvan Quan <evan.quan@amd.com> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
Some new variants require updated firmware. V2: add MODULE_FIRMWARE for new firmwares Reviewed-by: Huang Rui <ray.huang@amd.com> (v1) Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 YueHaibing 提交于
Remove some duplicated include. Signed-off-by: NYueHaibing <yuehaibing@huawei.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 01 11月, 2018 4 次提交
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由 Rex Zhu 提交于
print warning in dmesg to notify user the setting for sclk_od/mclk_od out of range that vbios can support Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Rex Zhu 提交于
not update dpm table with user's setting. Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Rex Zhu 提交于
not update the dpm table with user's setting Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
As MGPU fan boost feature will be definitely not needed when DPM is disabled. So, there is no need to error out. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 10月, 2018 1 次提交
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由 Evan Quan 提交于
Tell the version numbers when the pptable versions do not match. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 27 10月, 2018 1 次提交
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由 Shirish S 提交于
Currently send_msg_to_smc_async() only report which message failed, but the actual failing message is the previous one, which SMU is unable to service. This patch reads the contents of register where the SMU is stuck and report appropriately. v2: fix the build (Alex) Signed-off-by: NShirish S <shirish.s@amd.com> Reviewed-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 26 10月, 2018 2 次提交
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由 Evan Quan 提交于
So that it can be shared between all clocks. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu<Feifei.Xu@amd.com> Reviewed-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
Currently the clocks reported are in 10Khz unit. Correct them as Khz unit as DAL wanted. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu<Feifei.Xu@amd.com> Reviewed-by: NRex Zhu <Rex.Zhu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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