1. 14 6月, 2019 1 次提交
  2. 13 6月, 2019 1 次提交
  3. 12 6月, 2019 1 次提交
  4. 31 5月, 2019 1 次提交
  5. 29 5月, 2019 4 次提交
    • J
      Revert "drm/i915: Expand subslice mask" · a10f361d
      Jani Nikula 提交于
      This reverts commit 1ac159e2 ("drm/i915: Expand subslice mask"),
      which kills ICL due to GEM_BUG_ON() sanity checks before CI even gets a
      chance to do anything.
      
      The commit exposes an issue in commit 1e40d4ae ("drm/i915/cnl:
      Implement WaProgramMgsrForCorrectSliceSpecificMmioReads"), which will
      also need to be addressed.
      
      There's a proposed fix [1], but considering the seeming uncertainty with
      the fix as well as the size of the regressing commit (in this context,
      the one that actually brings down ICL), this warrants a revert to get
      ICL working, and gives us time to get all of this right without
      rushing. Even if this means shooting the messenger.
      
      <3>[    9.426327] intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu->max_slices)
      <4>[    9.426355] ------------[ cut here ]------------
      <2>[    9.426357] kernel BUG at drivers/gpu/drm/i915/gt/intel_sseu.c:46!
      <4>[    9.426371] invalid opcode: 0000 [#1] PREEMPT SMP NOPTI
      <4>[    9.426377] CPU: 1 PID: 364 Comm: systemd-udevd Not tainted 5.2.0-rc2-CI-CI_DRM_6159+ #1
      <4>[    9.426385] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3183.A00.1905020411 05/02/2019
      <4>[    9.426444] RIP: 0010:intel_sseu_get_subslices+0x8a/0xe0 [i915]
      <4>[    9.426452] Code: d5 76 b7 e0 48 8b 35 9d 24 21 00 49 c7 c0 07 f0 72 a0 b9 2e 00 00 00 48 c7 c2 00 8e 6d a0 48 c7 c7 a5 14 5b a0 e8 36 3c be e0 <0f> 0b 48 c7 c1 80 d5 6f a0 ba 30 00 00 00 48 c7 c6 00 8e 6d a0 48
      <4>[    9.426468] RSP: 0018:ffffc9000037b9c8 EFLAGS: 00010282
      <4>[    9.426475] RAX: 000000000000000f RBX: 0000000000000000 RCX: 0000000000000000
      <4>[    9.426482] RDX: 0000000000000001 RSI: 0000000000000008 RDI: ffff88849e346f98
      <4>[    9.426490] RBP: ffff88848a200000 R08: 0000000000000004 R09: ffff88849d50b000
      <4>[    9.426497] R10: 0000000000000000 R11: ffff88849e346f98 R12: ffff88848a209e78
      <4>[    9.426505] R13: 0000000003000000 R14: ffff88848a20b1a8 R15: 0000000000000000
      <4>[    9.426513] FS:  00007f73d5ae8680(0000) GS:ffff88849fc80000(0000) knlGS:0000000000000000
      <4>[    9.426521] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
      <4>[    9.426527] CR2: 0000561417b01260 CR3: 0000000494764003 CR4: 0000000000760ee0
      <4>[    9.426535] PKRU: 55555554
      <4>[    9.426538] Call Trace:
      <4>[    9.426585]  wa_init_mcr+0xd5/0x110 [i915]
      <4>[    9.426597]  ? lock_acquire+0xa6/0x1c0
      <4>[    9.426645]  icl_gt_workarounds_init+0x21/0x1a0 [i915]
      <4>[    9.426694]  ? i915_driver_load+0xfcf/0x18a0 [i915]
      <4>[    9.426739]  gt_init_workarounds+0x14c/0x230 [i915]
      <4>[    9.426748]  ? _raw_spin_unlock_irq+0x24/0x50
      <4>[    9.426789]  intel_gt_init_workarounds+0x1b/0x30 [i915]
      <4>[    9.426835]  i915_driver_load+0xfd7/0x18a0 [i915]
      <4>[    9.426843]  ? lock_acquire+0xa6/0x1c0
      <4>[    9.426850]  ? __pm_runtime_resume+0x4f/0x80
      <4>[    9.426857]  ? _raw_spin_unlock_irqrestore+0x4c/0x60
      <4>[    9.426863]  ? _raw_spin_unlock_irqrestore+0x4c/0x60
      <4>[    9.426870]  ? lockdep_hardirqs_on+0xe3/0x1b0
      <4>[    9.426915]  i915_pci_probe+0x29/0xa0 [i915]
      <4>[    9.426923]  pci_device_probe+0x9e/0x120
      <4>[    9.426930]  really_probe+0xea/0x3c0
      <4>[    9.426936]  driver_probe_device+0x10b/0x120
      <4>[    9.426942]  device_driver_attach+0x4a/0x50
      <4>[    9.426948]  __driver_attach+0x97/0x130
      <4>[    9.426954]  ? device_driver_attach+0x50/0x50
      <4>[    9.426960]  bus_for_each_dev+0x74/0xc0
      <4>[    9.426966]  bus_add_driver+0x13f/0x210
      <4>[    9.426971]  ? 0xffffffffa083b000
      <4>[    9.426976]  driver_register+0x56/0xe0
      <4>[    9.426982]  ? 0xffffffffa083b000
      <4>[    9.426987]  do_one_initcall+0x58/0x300
      <4>[    9.426994]  ? do_init_module+0x1d/0x1f6
      <4>[    9.427001]  ? rcu_read_lock_sched_held+0x6f/0x80
      <4>[    9.427007]  ? kmem_cache_alloc_trace+0x261/0x290
      <4>[    9.427014]  do_init_module+0x56/0x1f6
      <4>[    9.427020]  load_module+0x24d1/0x2990
      <4>[    9.427032]  ? __se_sys_finit_module+0xd3/0xf0
      <4>[    9.427037]  __se_sys_finit_module+0xd3/0xf0
      <4>[    9.427047]  do_syscall_64+0x55/0x1c0
      <4>[    9.427053]  entry_SYSCALL_64_after_hwframe+0x49/0xbe
      <4>[    9.427059] RIP: 0033:0x7f73d5609839
      <4>[    9.427064] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48
      <4>[    9.427082] RSP: 002b:00007ffdf34477b8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
      <4>[    9.427091] RAX: ffffffffffffffda RBX: 00005559fd5d7b40 RCX: 00007f73d5609839
      <4>[    9.427099] RDX: 0000000000000000 RSI: 00007f73d52e8145 RDI: 000000000000000f
      <4>[    9.427106] RBP: 00007f73d52e8145 R08: 0000000000000000 R09: 00007ffdf34478d0
      <4>[    9.427114] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000
      <4>[    9.427121] R13: 00005559fd5c90f0 R14: 0000000000020000 R15: 00005559fd5d7b40
      <4>[    9.427131] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp snd_hda_intel crct10dif_pclmul crc32_pclmul snd_hda_codec snd_hwdep e1000e snd_hda_core ghash_clmulni_intel ptp snd_pcm cdc_ether usbnet mii pps_core mei_me mei prime_numbers btusb btrtl btbcm btintel bluetooth ecdh_generic ecc
      <4>[    9.427254] ---[ end trace af3eeb543bd66e66 ]---
      
      [1] http://patchwork.freedesktop.org/patch/msgid/20190528200655.11605-1-chris@chris-wilson.co.uk
      
      References: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/fi-icl-u2/pstore0-1517155098_Oops_1.log
      References: 1e40d4ae ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")
      Fixes: 1ac159e2 ("drm/i915: Expand subslice mask")
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
      Cc: Manasi Navare <manasi.d.navare@intel.com>
      Cc: Michel Thierry <michel.thierry@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Cc: Oscar Mateo <oscar.mateo@intel.com>
      Cc: Stuart Summers <stuart.summers@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Cc: Yunwei Zhang <yunwei.zhang@intel.com>
      Acked-by: NDaniel Vetter <daniel@ffwll.ch>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190529082150.31526-1-jani.nikula@intel.com
      a10f361d
    • S
      drm/i915: Expand subslice mask · 1ac159e2
      Stuart Summers 提交于
      Currently, the subslice_mask runtime parameter is stored as an
      array of subslices per slice. Expand the subslice mask array to
      better match what is presented to userspace through the
      I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
      then calculated:
        slice * subslice stride + subslice index / 8
      
      v2: fix spacing in set_sseu_info args
          use set_sseu_info to initialize sseu data when building
          device status in debugfs
          rename variables in intel_engine_types.h to avoid checkpatch
          warnings
      v3: update headers in intel_sseu.h
      v4: add const to some sseu_dev_info variables
          use sseu->eu_stride for EU stride calculations
      v5: address review comments from Tvrtko and Daniele
      v6: remove extra space in intel_sseu_get_subslices
          return the correct subslice enable in for_each_instdone
          add GEM_BUG_ON to ensure user doesn't pass invalid ss_mask size
          use printk formatted string for subslice mask
      v7: remove string.h header and rebase
      
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
      Acked-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Reviewed-by: NDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Signed-off-by: NStuart Summers <stuart.summers@intel.com>
      Signed-off-by: NManasi Navare <manasi.d.navare@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190524154022.13575-6-stuart.summers@intel.com
      1ac159e2
    • S
      drm/i915: Refactor sseu helper functions · 0040fd19
      Stuart Summers 提交于
      Move functions to intel_sseu.h and remove inline qualifier.
      Additionally, ensure these are all prefixed with intel_sseu_*
      to match the convention of other functions in i915.
      
      v2: fix spacing from checkpatch warning
      v3: squash helper function changes into a single patch
          break 80 character line to fix checkpatch warning
          move get/set_eus helpers to intel_device_info.c
      v4: Remove intel_ prefix from static functions in
          intel_device_info.c and correctly copy changes
          to stride calculation in those functions.
      Acked-by: NJani Nikula <jani.nikula@intel.com>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Reviewed-by: NDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Signed-off-by: NStuart Summers <stuart.summers@intel.com>
      Signed-off-by: NManasi Navare <manasi.d.navare@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190524154022.13575-5-stuart.summers@intel.com
      0040fd19
    • S
      drm/i915: Use local variable for SSEU info in GETPARAM ioctl · bd41ca49
      Stuart Summers 提交于
      In the GETPARAM ioctl handler, use a local variable to consolidate
      usage of SSEU runtime info.
      
      v2: add const to sseu_dev_info variable
      
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Reviewed-by: NDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Signed-off-by: NStuart Summers <stuart.summers@intel.com>
      Signed-off-by: NManasi Navare <manasi.d.navare@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190524154022.13575-2-stuart.summers@intel.com
      bd41ca49
  6. 28 5月, 2019 3 次提交
  7. 22 5月, 2019 2 次提交
  8. 08 5月, 2019 1 次提交
  9. 03 5月, 2019 4 次提交
  10. 30 4月, 2019 3 次提交
  11. 26 4月, 2019 1 次提交
  12. 25 4月, 2019 2 次提交
    • C
      drm/i915: Invert the GEM wakeref hierarchy · 79ffac85
      Chris Wilson 提交于
      In the current scheme, on submitting a request we take a single global
      GEM wakeref, which trickles down to wake up all GT power domains. This
      is undesirable as we would like to be able to localise our power
      management to the available power domains and to remove the global GEM
      operations from the heart of the driver. (The intent there is to push
      global GEM decisions to the boundary as used by the GEM user interface.)
      
      Now during request construction, each request is responsible via its
      logical context to acquire a wakeref on each power domain it intends to
      utilize. Currently, each request takes a wakeref on the engine(s) and
      the engines themselves take a chipset wakeref. This gives us a
      transition on each engine which we can extend if we want to insert more
      powermangement control (such as soft rc6). The global GEM operations
      that currently require a struct_mutex are reduced to listening to pm
      events from the chipset GT wakeref. As we reduce the struct_mutex
      requirement, these listeners should evaporate.
      
      Perhaps the biggest immediate change is that this removes the
      struct_mutex requirement around GT power management, allowing us greater
      flexibility in request construction. Another important knock-on effect,
      is that by tracking engine usage, we can insert a switch back to the
      kernel context on that engine immediately, avoiding any extra delay or
      inserting global synchronisation barriers. This makes tracking when an
      engine and its associated contexts are idle much easier -- important for
      when we forgo our assumed execution ordering and need idle barriers to
      unpin used contexts. In the process, it means we remove a large chunk of
      code whose only purpose was to switch back to the kernel context.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Imre Deak <imre.deak@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
      79ffac85
    • C
      drm/i915: Move GraphicsTechnology files under gt/ · 112ed2d3
      Chris Wilson 提交于
      Start partitioning off the code that talks to the hardware (GT) from the
      uapi layers and move the device facing code under gt/
      
      One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to
      subdivide that header and body further (and split out the submission
      code from the ringbuffer and logical context handling). This patch aims
      to be simple motion so git can fixup inflight patches with little mess.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Acked-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Acked-by: NJani Nikula <jani.nikula@intel.com>
      Acked-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
      112ed2d3
  13. 20 4月, 2019 1 次提交
  14. 19 4月, 2019 1 次提交
  15. 08 4月, 2019 7 次提交
  16. 06 4月, 2019 1 次提交
  17. 03 4月, 2019 2 次提交
  18. 02 4月, 2019 1 次提交
    • T
      drm/i915: Introduce concept of a sub-platform · 805446c8
      Tvrtko Ursulin 提交于
      Concept of a sub-platform already exist in our code (like ULX and ULT
      platform variants and similar),implemented via the macros which check a
      list of device ids to determine a match.
      
      With this patch we consolidate device ids checking into a single function
      called during early driver load.
      
      A few low bits in the platform mask are reserved for sub-platform
      identification and defined as a per-platform namespace.
      
      At the same time it future proofs the platform_mask handling by preparing
      the code for easy extending, and tidies the very verbose WARN strings
      generated when IS_PLATFORM macros are embedded into a WARN type
      statements.
      
      v2: Fixed IS_SUBPLATFORM. Updated commit msg.
      v3: Chris was right, there is an ordering problem.
      
      v4:
       * Catch-up with new sub-platforms.
       * Rebase for RUNTIME_INFO.
       * Drop subplatform mask union tricks and convert platform_mask to an
         array for extensibility.
      
      v5:
       * Fix subplatform check.
       * Protect against forgetting to expand subplatform bits.
       * Remove platform enum tallying.
       * Add subplatform to error state. (Chris)
       * Drop macros and just use static inlines.
       * Remove redundant IRONLAKE_M. (Ville)
      
      v6:
       * Split out Ironlake change.
       * Optimize subplatform check.
       * Use __always_inline. (Lucas)
       * Add platform_mask comment. (Paulo)
       * Pass stored runtime info in error capture. (Chris)
      
      v7:
       * Rebased for new AML ULX device id.
       * Bump platform mask array size for EHL.
       * Stop mentioning device ids in intel_device_subplatform_init by using
         the trick of splitting macros i915_pciids.h. (Jani)
       * AML seems to be either a subplatform of KBL or CFL so express it like
         that.
      
      v8:
       * Use one device id table per subplatform. (Jani)
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Suggested-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Lucas De Marchi <lucas.demarchi@intel.com>
      Cc: Jose Souza <jose.souza@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Acked-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190327142328.31780-1-tvrtko.ursulin@linux.intel.com
      805446c8
  19. 29 3月, 2019 1 次提交
  20. 27 3月, 2019 2 次提交