- 11 1月, 2020 1 次提交
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由 Yishai Hadas 提交于
Add Virtio Emulation related fields to the device capabilities. It includes a general bit to indicate whether Virtio Emulation is supported and the capabilities structure itself. Signed-off-by: NYishai Hadas <yishaih@mellanox.com> Reviewed-by: NShahaf Shuler <shahafs@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
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- 23 11月, 2019 1 次提交
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由 Yevgeny Kliteynik 提交于
Add definition for flex parser tunneling header for Geneve. Signed-off-by: NYevgeny Kliteynik <kliteyn@mellanox.com> Reviewed-by: NAlex Vesker <valex@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 30 10月, 2019 1 次提交
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由 Roi Dayan 提交于
The union should contain the extended dest and counter list. Remove the resevered 0x40 bits which is redundant. This change doesn't break any functionally. Everything works today because the code in fs_cmd.c is using the correct structs if extended dest or the basic dest. Fixes: 1b115498 ("net/mlx5: Introduce extended destination fields") Signed-off-by: NRoi Dayan <roid@mellanox.com> Reviewed-by: NMark Bloch <markb@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 08 10月, 2019 1 次提交
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由 Yamin Friedman 提交于
Expose maximum scatter entries per RDMA READ for optimal performance. Signed-off-by: NYamin Friedman <yaminf@mellanox.com> Reviewed-by: NOr Gerlitz <ogerlitz@mellanox.com> Reviewed-by: NChristoph Hellwig <hch@lst.de> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
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- 24 9月, 2019 1 次提交
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由 Yevgeny Kliteynik 提交于
Fix wrong reserved bits offsets. Fixes: 97b5484e ("net/mlx5: Add HW bits and definitions required for SW steering") Signed-off-by: NYevgeny Kliteynik <kliteyn@mellanox.com> Reviewed-by: NAlex Vesker <valex@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 06 9月, 2019 1 次提交
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由 Aya Levin 提交于
Map capability bit indicating that HCA supports port buffer's congestion counters. Also map registers with the corresponding counters. Signed-off-by: NAya Levin <ayal@mellanox.com> Reviewed-by: NMoshe Shemesh <moshe@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 02 9月, 2019 1 次提交
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由 Alex Vesker 提交于
Add the required Software Steering hardware definitions and bits to mlx5_ifc. Signed-off-by: NAlex Vesker <valex@mellanox.com> Signed-off-by: NYevgeny Klitenik <kliten@mellanox.com> Reviewed-by: NMark Bloch <markb@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 28 8月, 2019 1 次提交
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由 Michael Guralnik 提交于
In mlx5_core initialization, query max ODP capabilities for DC transport from FW and set as current capabilities. Signed-off-by: NMichael Guralnik <michaelgur@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
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- 21 8月, 2019 3 次提交
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由 Maxim Mikityanskiy 提交于
Add the lag_tx_port_affinity HCA capability bit that indicates that setting port affinity of TISes is supported. Signed-off-by: NMaxim Mikityanskiy <maximmi@mellanox.com> Reviewed-by: NTariq Toukan <tariqt@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Aya Levin 提交于
Expose Fw indication that it supports Stateless Offloads for IP over IP tunneled packets. The following offloads are supported for the inner packets: RSS, RX & TX Checksum Offloads, LSO and Flow Steering. Signed-off-by: NAya Levin <ayal@mellanox.com> Reviewed-by: NTariq Toukan <tariqt@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Moshe Shemesh 提交于
Add mlx5 interface support for reading internal rq out of buffer counter as part of QUERY_VNIC_ENV command. The command is used by the driver to query vnic diagnostic statistics from FW. Signed-off-by: NMoshe Shemesh <moshe@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 13 8月, 2019 1 次提交
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由 Yishai Hadas 提交于
Add XRQ legacy commands opcodes, will be used via the DEVX interface. Signed-off-by: NYishai Hadas <yishaih@mellanox.com> Reviewed-by: NSaeed Mahameed <saeedm@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
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- 09 8月, 2019 1 次提交
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由 Tariq Toukan 提交于
The TLS progress params context WQE should not include an Eth segment, drop it. In addition, align the tls_progress_params layout with the HW specification document: - fix the tisn field name. - remove the valid bit. Fixes: a12ff35e ("net/mlx5: Introduce TLS TX offload hardware bits and structures") Fixes: d2ead1f3 ("net/mlx5e: Add kTLS TX HW offload support") Signed-off-by: NTariq Toukan <tariqt@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 04 8月, 2019 1 次提交
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由 Mark Zhang 提交于
Remove the "reserved_at_40" field to match the device specification. Fixes: 84df61eb ("net/mlx5: Add HW interfaces used by LAG") Signed-off-by: NMark Zhang <markz@mellanox.com> Reviewed-by: NYishai Hadas <yishaih@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
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- 02 8月, 2019 3 次提交
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由 Eli Cohen 提交于
Check if firmware supports the requested element type before attempting to create the element type. In addition, explicitly specify the request element type and tsar type. Signed-off-by: NEli Cohen <eli@mellanox.com> Reviewed-by: NPaul Blakey <paulb@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Saeed Mahameed 提交于
First reserved field is off by one instead of reserved_at_1 it should be reserved_at_2, fix that. Fixes: a12ff35e ("net/mlx5: Introduce TLS TX offload hardware bits and structures") Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com> Reviewed-by: NLeon Romanovsky <leonro@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Gavi Teitz 提交于
Add a handle to invoke the new FW capability of allocating a bulk of flow counters. Signed-off-by: NGavi Teitz <gavi@mellanox.com> Reviewed-by: NVlad Buslov <vladbu@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 26 7月, 2019 1 次提交
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由 Edward Srouji 提交于
Fix modify_cq_in alignment to match the device specification. After this fix the 'cq_umem_valid' field will be in the right offset. Cc: <stable@vger.kernel.org> # 4.19 Fixes: bd371975 ("net/mlx5: Update mlx5_ifc with DEVX UID bits") Signed-off-by: NEdward Srouji <edwards@mellanox.com> Reviewed-by: NYishai Hadas <yishaih@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 12 7月, 2019 1 次提交
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由 Saeed Mahameed 提交于
CQE checksum full mode in new HW, provides a full checksum of rx frame. Covering bytes starting from eth protocol up to last byte in the received frame (frame_size - ETH_HLEN), as expected by the stack. Fixing up skb->csum by the driver is not required in such case. This fix is to avoid wrong checksum calculation in drivers which already support the new hardware with the new checksum mode. Fixes: 85327a9c ("net/mlx5: Update the list of the PCI supported devices") Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 07 7月, 2019 1 次提交
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由 Max Gurtovoy 提交于
When using the device emulation feature (introduced in Bluefield-1 SOC), a privileged function (the device emulation manager) will be able to create a channel to execute commands on behalf of the emulated function. This channel will be a general object of type VHCA_TUNNEL that will have a unique ID for each emulated function. This ID will be passed in each cmd that will be issued by the emulation SW in a well known offset in the command header. This channel is needed since the emulated function doesn't have a normal command interface to the HCA HW, but some basic configuration for that function is needed (e.g. initialize and enable the HCA). For that matter, a specific command-set was defined and only those commands will be issued by the HCA. Signed-off-by: NMax Gurtovoy <maxg@mellanox.com> Reviewed-by: NYishai Hadas <yishaih@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
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- 05 7月, 2019 1 次提交
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由 Mark Zhang 提交于
Add rts2rts_qp_counters_set_id field in hca cap so that RTS2RTS qp modification can be used to change the counter of a QP. Signed-off-by: NMark Zhang <markz@mellanox.com> Reviewed-by: NMajd Dibbiny <majd@mellanox.com> Acked-by: NSaeed Mahameed <saeedm@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
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- 04 7月, 2019 3 次提交
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由 Eran Ben Elisha 提交于
Add TLS offload related IFC structs, layouts and enumerations. Signed-off-by: NEran Ben Elisha <eranbe@mellanox.com> Signed-off-by: NTariq Toukan <tariqt@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Yishai Hadas 提交于
Expose an extra device definitions for objects events. It includes: object_type values for legacy objects and generic data header for any other object. Signed-off-by: NYishai Hadas <yishaih@mellanox.com> Acked-by: NSaeed Mahameed <saeedm@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
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由 Yishai Hadas 提交于
Use the reported device capabilities for the supported user events (i.e. affiliated and un-affiliated) to set the EQ mask. As the event mask can be up to 256 defined by 4 entries of u64 change the applicable code to work accordingly. Signed-off-by: NYishai Hadas <yishaih@mellanox.com> Acked-by: NSaeed Mahameed <saeedm@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com>
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- 02 7月, 2019 3 次提交
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由 Bodong Wang 提交于
When ECPF eswitch manager is at offloads mode, it monitors functions changed event from host PF side and acts according to the number of VFs enabled/disabled. As ECPF and host PF work in two independent hosts, it's possible that host PF OS reboots but ECPF system is still kept on and continues monitoring events from host PF. When kernel from host PF side is booting, PCI iov driver does sriov_init and compute_max_vf_buses by iterating over all valid num of VFs. This triggers FLR and generates functions changed events, even though host PF HCA is not enabled at this time. However, ECPF is not aware of this information, and still handles these events as usual. ECPF system will see massive number of reps are created, but destroyed immediately once creation finished. To eliminate this noise, a bit is added to host parameter context to indicate host PF is disabled. ECPF will not handle the VF changed event if this bit is set. Signed-off-by: NBodong Wang <bodong@mellanox.com> Reviewed-by: NDaniel Jurgens <danielj@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Shay Agroskin 提交于
Given a fw component index, the MCQI register allows us to query this component's information (e.g. its version and capabilities). Given a fw component index, the MCQS register allows us to query the status of a fw component, including its type and state (e.g. PRESET/IN_USE). It can be used to find the index of a component of a specific type, by sequentially increasing the component index, and querying each time the type of the returned component. If max component index is reached, 'last_index_flag' is set by the HCA. These registers' description was added to query the running and pending fw version of the HCA. Signed-off-by: NShay Agroskin <shayag@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Parav Pandit 提交于
Update mlx5 device interface data structures for: 1. New command definitions for allocating, deallocating SF 2. Query SF partition 3. Eswitch SF fields 4. HCA CAP SF fields 5. Extend Eswitch functions command for SF Signed-off-by: NParav Pandit <parav@mellanox.com> Signed-off-by: NVu Pham <vuhuong@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 27 6月, 2019 1 次提交
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由 Jianbo Liu 提交于
When a dual-port VHCA sends a RoCE packet on its non-native port, and the packet arrives to its affiliated vport FDB, a mismatch might occur on the rules that match the packet source vport. So we replace the match on source port with the match on metadata that was configured in ingress ACL, and that metadata will be passed further also to the NIC RX table of the eswitch manager. Introduce vport metadata matching bits and enum constants as a pre-step towards metadata matching. o metadata type C registers in the misc parameters 2 fields. o esw_uplink_ingress_acl bit in esw cap. If it set, the device supports ingress ACL for the uplink vport. o fdb_to_vport_reg_* bits in flow table cap and esw vport context, to support propagating the metadata to the nic rx through the loopback path. o flow_source in flow context, to indicate the known origin of packets. o enum constants, to support the above bits. Signed-off-by: NJianbo Liu <jianbol@mellanox.com> Reviewed-by: NEli Britstein <elibr@mellanox.com> Reviewed-by: NRoi Dayan <roid@mellanox.com> Reviewed-by: NMark Bloch <markb@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 14 6月, 2019 1 次提交
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由 Bodong Wang 提交于
For ECPF with eswitch manager privilege, query the host max VF count by querying the device using query_functions command. With this enhancement: 1. flow steering entries are created only for valid vports based on the max VF count of the PF. 2. Driver only queries cap of valid vport. Eswitch requires the max VFs when doing initialization, so do sr-iov init before eswitch init. Signed-off-by: NBodong Wang <bodong@mellanox.com> Reviewed-by: NParav Pandit <parav@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 01 6月, 2019 4 次提交
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由 Vu Pham 提交于
Whenever device supports eswitch functions changed event, honor such device setting. Do not limit it to ECPF. Signed-off-by: NParav Pandit <parav@mellanox.com> Signed-off-by: NVu Pham <vuhuong@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Vu Pham 提交于
To support sriov on a E-Switch manager, num_vfs are queried to the firmware whenever E-Switch manager is notified by esw_functions_changed event. Replace host_params event with esw_functions_changed event that reflects more appropriate naming. While at it, also correct num_vfs type from int to u16 as expected by the function mlx5_esw_query_functions(). Signed-off-by: NVu Pham <vuhuong@mellanox.com> Reviewed-by: NParav Pandit <parav@mellanox.com> Reviewed-by: NBodong Wang <bodong@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Eli Britstein 提交于
Termination table is a flow table with a termination flag. The flag allows the firmware to assume that the the specified actions are the last actions list. This assumption allows the FW to safely perform potential looping logic (e.g. hairpin). Introduce the bits for this attribute. Signed-off-by: NEli Britstein <elibr@mellanox.com> Reviewed-by: NOz Shlomo <ozsh@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Moshe Shemesh 提交于
Add Firmware core dump registers and HW definitions. Signed-off-by: NMoshe Shemesh <moshe@mellanox.com> Signed-off-by: NEran Ben Elisha <eranbe@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 14 5月, 2019 1 次提交
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由 Yishai Hadas 提交于
Mark completion EQs as shared resources so that they can be used by CQs with uid != 0. Fixes: 7efce369 ("IB/mlx5: Add obj create and destroy functionality") Signed-off-by: NYishai Hadas <yishaih@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com> Signed-off-by: NLeon Romanovsky <leonro@mellanox.com> Signed-off-by: NJason Gunthorpe <jgg@mellanox.com>
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- 02 5月, 2019 1 次提交
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由 Saeed Mahameed 提交于
The cited commit broke the offsets of hca cap struct, fix it. While at it, cleanup a white space introduced by the same commit. Fixes: b169e64a ("net/mlx5: Geneve, Add flow table capabilities for Geneve decap with TLV options") Reported-by: NQian Cai <cai@lca.pw> Cc: Yevgeny Kliteynik <kliteyn@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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- 30 4月, 2019 5 次提交
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由 Yevgeny Kliteynik 提交于
Introduce specification for Geneve decap flow with encapsulation options and allow creation of rules that are matching on Geneve TLV options. Reviewed-by: NOz Shlomo <ozsh@mellanox.com> Signed-off-by: NYevgeny Kliteynik <kliteyn@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Yevgeny Kliteynik 提交于
Introduce support for Geneve flow specification and allow the creation of rules that are matching on basic Geneve protocol fields: VNI, OAM bit, protocol type, options length. Reviewed-by: NOz Shlomo <ozsh@mellanox.com> Signed-off-by: NYevgeny Kliteynik <kliteyn@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Maor Gottlieb 提交于
Flow table supports three types of miss action: 1. Default miss action - go to default miss table according to table. 2. Go to specific table. 3. Switch domain - go to the root table of an alternative steering table domain. New table miss action was added - switch_domain. The next domain for RDMA_RX namespace is the NIC RX domain. Signed-off-by: NMaor Gottlieb <maorg@mellanox.com> Reviewed-by: NMark Bloch <markb@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Maor Gottlieb 提交于
Add new flow steering namespace - MLX5_FLOW_NAMESPACE_RDMA_RX. Flow steering rules in this namespace are used to filter RDMA traffic. Signed-off-by: NMaor Gottlieb <maorg@mellanox.com> Reviewed-by: NMark Bloch <markb@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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由 Eli Britstein 提交于
Current ConnectX HW is unable to perform VLAN pop in TX path and VLAN push on RX path. To workaround that limitation untagged packets will be tagged with VLAN ID 0x000 (priority tag) and pop/push actions will be replaced by VLAN re-write actions (which are supported by the HW). Introduce prio tag mode as a pre-step to controlling the workaround behavior. Signed-off-by: NEli Britstein <elibr@mellanox.com> Reviewed-by: NOz Shlomo <ozsh@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
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