The Orange Pi Plus board lacks voltage scaling capabilities in its
current form. This results in random freezes during boot when cpufreq is
enabled, probably due to wrong voltages.

This patch (more or less copy/paste from 06139c) does the following
things on this board:
- enable r_i2c
- add sy8106a to the r_i2c bus
- have the sy8106a regulate VDD of cpu

Since the Orange Pi Plus has the same PMU setup as the Orange Pi PC, I
simply took min/max/fixed/ramp from the latter DTS. In that file the
origin of the values are described by the following comment:

  "The datasheet uses 1.1V as the minimum value of VDD-CPUX,
  however both the Armbian DVFS table and the official one
  have operating points with voltage under 1.1V, and both
  DVFS table are known to work properly at the lowest
  operating point.
  Use 1.0V as the minimum voltage instead."

I have tested this on patch two Orange Pi Plus boards, by running a
kernel with this patch and do intermettent runs of cpuburn while
monitoring voltage, frequency and temperature. The board runs stable
across its operatiing points while showing a reasonable (< 40C)
temperature. My Orange Pi PC, when put to the same test, yields similar
stable results.
Signed-off-by: NJorik Jonker <jorik@kippendief.biz>
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>

Remove unused parameter from HASH1 dmas property on stm32mp157c SoC.

Fixes: 1e726a40 ("ARM: dts: stm32: Add HASH support on stm32mp157c")
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>
[Olof: Bug doesn't cause any harm, so shouldn't need stable backport]
Signed-off-by: NOlof Johansson <olof@lixom.net>

Not all boards use two ethernet devices and/or use them in different
order. As almost all in-tree boards already define their own ethernet
aliases, remove them from the dtsi and add the aliases to the two boards,
that are missing their own definition.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
[dinguyen@kernel.org: rebased to latest dts changes]
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>

This is required for the imx pci driver to send the PME_Turn_Off TLP.
Signed-off-by: NLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>

As the v4l2-fwnode now allows drivers to set defaults, and eventually
override them by specifying properties in DTS, use defaults for the CEU
driver.

Also remove endpoint properties from the gr-peach-audiocamerashield as
they match the defaults now specified in the driver code
(h/vsync-active and bus-width) or are not relevant to the interface
as they cannot be configured (pclk-sample).
Signed-off-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: NSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab+samsung@kernel.org>

This board has a Micron MT29F8G08ABACAWP chip which requires a ECC
strength of 8/512. Rather than hard coding any particular strength the
the nand controller auto-detect the ECC strength based on the ONFI data.
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Due to the electrical design of the A/DC circuits on LEGO MINDSTORMS EV3,
if we are reading analog values as fast as possible (i.e. using DMA to
service the SPI) the A/DC chip will read incorrect values - as much as
0.1V off when the SPI is running at 10MHz. (This has to do with the
capacitor charge time when channels are muxed in the A/DC.)

This patch slows down the SPI as much as possible (if CPU is at 456MHz,
SPI runs at 1/2 of that, so 228MHz and has a max prescalar of 256, so
we could get ~891kHz, but we're just rounding it to 1MHz). We also use
the max allowable value for WDELAY to slow things down even more.

These changes reduce the error of the analog values to about 5mV, which
is tolerable.

Commits a3762b13 ("spi: spi-davinci: Add support for SPI_CS_WORD")
and e2540da8 ("iio: adc: ti-ads7950: use SPI_CS_WORD to reduce
CPU usage") introduce changes that allow DMA transfers to be used, so
this slow down is needed now.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

There is a GPIO expander on both the UI board as well as the
baseboard.  This patch enables the second tca6416 and identifies
it as being on the baseboard using _bb as the suffix.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add nodes of USB2 physical layer for UniPhier SoC. This supports Pro4.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add USB3 controller nodes including usb-core, resets, regulator, ss-phy
and hs-phy. This supports for Pro4, PXs2 and the boards.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

sama5d4_xplained, ssam9x5cm, sama5d2_ptc_ek and sama5d3_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our NAND flash map available at:

http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.pngSigned-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>

sama5d3_xplained, sam9x5cm, sama5d2_ptc_ek and sama5d4_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our nand flash map available at:

http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.pngSigned-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>

sam9x5cm, sama5d2_ptc_ek, sama5d3_xplained and sama5d4_xplained nand
flashes have a common memory map. Even the nand memory partitions to
match our nand flash map available at:

http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.pngSigned-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>

The offsets for the bootloader environment and its redundant partition
were inverted. Fix the addresses to match our nand flash map available at:

http://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections//demo_nandflash_map_lnx4sam5x.pngSigned-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>

at91sam9x5cm comes with a 2Gb NAND flash. Fix the rootfs size to
match this limit.
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>

sama5d4_xplained comes with a 4Gb NAND flash. Increase the rootfs
size to match this limit.
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>

Add SD controller nodes for LD4, Pro4, sLD8, Pro5, and PXs2.
This is also used as an eMMC controller for LD4, Pro4, and sLD8.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add SD card write-protect pin configuration to be sure that it will be
properly pulled down to indicate write access.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

Switch to the new hardware port bindings for coresight

Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

i.MX6ULZ is new SoC of i.MX6 family, compared to i.MX6ULL,
it removes below modules:

- UART5/UART6/UART7/UART8;
- PWM5/PWM6/PWM7/PWM8;
- eCSPI3/eCSPI4;
- CAN1/CAN2;
- FEC1/FEC2;
- I2C3/I2C4;
- EPIT2;
- LCDIF;
- GPT2;
- ADC1;
- TSC;

This patch adds support for i.MX6ULZ and i.MX6ULZ 14x14 EVK
board.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The 'num-chipselects' property is not a valid property according
to Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt, so
let's remove it.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Bananapi released an updated revision of the H3/H5 based Bananapi M2+.
Version 1.2 enables voltage control for the CPU's regulator by using
a GPIO line to toggle a MOSFET that can change the effective resistance
value in the regulator's feedback network.

This patch adds a common .dtsi file for this new revision, which
includes the original common sunxi-bananapi-m2-plus.dtsi file, and
adds the GPIO-controlled regulator and a cpu-supply reference. H3
and H5 variant dts files are added as well.
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

This adds nodes for the Video Engine and the associated reserved memory
for the H3. Up to 96 MiB of memory are dedicated to the CMA pool.
Signed-off-by: NPaul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>

Three more variants of the Bananapi M2 Plus have been introduced. One
with the H5 instead of the H3, another with the H2+ instead, and the
last with the H3 but with WiFi and eMMC removed.

All these variants use the same board. This patch splits out the
non-SoC-specific parts of the device tree, so that they can be shared
among all the variants. The original Bananapi M2 Plus has been renamed
to Bananapi M2 Plus H3.
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

The external RTL8211E RGMII Ethernet PHY is configured via external
resistors to use the address 0x1. The 0x0 address is a broadcast address
for this family of PHYs, and should not be used explicitly.

Fixes: 8c7ba536 ("ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i")
Fixes: 4904337f ("ARM: dts: sunxi: Restore EMAC changes (boards)")
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: NPhilipp Rossak <embed3d@gmail.com>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>

Orangepi Zero Plus 2 is an open-source single-board computer, available in two
Allwinner SOC variants, H3 and H5. We add support for H3 variant here, as the
H5 is already supported by sun50i-h5-orangepi-zero-plus2.dts.

H3 Orangepi Zero Plus 2 has:
- Quad-core Cortex-A7
- 512MB DDR3
- microSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG + power supply
Signed-off-by: NDiego Rondini <diego.rondini@kynetics.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@bootlin.com>

Looks like we still have two instances of phy_handle that did not
get update by Grygorii's series. Let's replace these too with
standard phy-handle.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Neeraj Dantu <dantuguf14105@gmail.com>
Reported-by: NArnd Bergmann <arnd@arndb.de>
Reviewed-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Acked-by: NKoen Kooi <koen@dominion.thruhere.net>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add support for Moxa UC-2101 open platform

The UC-2101 computing platform is designed for industrial embedded
data acquisition and processing applications.

The features of UC-2101 are:
* eMMC
* SPI flash
* 1x LAN
* 1x RS-232/422/485 ports, software-selectable
* EEPROM
* TPM 2.0
* Watchdog
* RTC
* User gpio-keys
* User LEDs
* User button
Signed-off-by: NWes Huang (黃淵河) <wes.huang@moxa.com>
Signed-off-by: NFero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
Signed-off-by: NSZ Lin (林上智) <sz.lin@moxa.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The UC-2100 series consists many boards with different peripheral
devices and wireless modules, hence we fetch common items and
create a common dtsi file to increase reusability. All boards in
UC-2100 series will include this common dtsi file.
Signed-off-by: NWes Huang (黃淵河) <wes.huang@moxa.com>
Signed-off-by: NFero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
Signed-off-by: NSZ Lin (林上智) <sz.lin@moxa.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Since SMPS10 and OTG cable detection extcon are described here, and
work to enable OTG power when an OTG cable is plugged in, we can
define OTG mode in the controller (which is disabled by default in
omap5.dtsi).

Tested on OMAP5EVM and Pyra.
Suggested-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NH. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add ti,syscon-unaligned-access property to PCIe RC nodes to set
appropriate bits in CTRL_CORE_SMA_SW_7 register to enable workaround for
errata i870.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.

Fixes: d23f3839 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
Cc: stable@vger.kernel.org
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the
name enables dtc SPI bus checks.

Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

PCIe is not populated by default on iWave RZ/G1N board. RZ/G1N board
is almost identical to RZ/G1M. In order to reuse the common dtsi for
both the boards, it is required to move pcie node from common dtsi
to board specific dts.
Signed-off-by: NBiju Das <biju.das@bp.renesas.com>
Reviewed-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add I2C4 support to RZ/G1C (a.k.a. r8a77470) SoC specific
device tree.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das@bp.renesas.com>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add SoC specific device tree definitions for the SDHI2 interface.
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das@bp.renesas.com>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".
Signed-off-by: NFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das@bp.renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>