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  1. 13 5月, 2016 1 次提交
  3. 17 3月, 2016 1 次提交
    • F
      Watchdog: introduce ARM SBSA watchdog driver · 57d2caaa
      由 Fu Wei 提交于 
      According to Server Base System Architecture (SBSA) specification,
the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0)
is for alerting the system by interrupt, the second one (WS1) is a real
hardware reset.
More details about the hardware specification of this device:
ARM DEN0029B - Server Base System Architecture (SBSA)

This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
or a two stages watchdog, it's set up by the module parameter "action".
In the single stage mode, when the timeout is reached, your system
will be reset by WS1. The first signal (WS0) is ignored.
In the two stages mode, when the timeout is reached, the first signal (WS0)
will trigger panic. If the system is getting into trouble and cannot be reset
by panic or restart properly by the kdump kernel(if supported), then the
second stage (as long as the first stage) will be reached, system will be
reset by WS1. This function can help administrator to backup the system
context info by panic console output or kdump.

This driver bases on linux kernel watchdog framework, so it can get
timeout from module parameter and FDT at the driver init stage.
Signed-off-by: NFu Wei <fu.wei@linaro.org>
Reviewed-by: NGraeme Gregory <graeme.gregory@linaro.org>
Tested-by: NPratyush Anand <panand@redhat.com>
Acked-by: NTimur Tabi <timur@codeaurora.org>
Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Tested-by: NSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      57d2caaa
  5. 01 3月, 2016 2 次提交
  7. 07 2月, 2016 1 次提交
  9. 01 2月, 2016 1 次提交
  11. 10 1月, 2016 1 次提交
  13. 29 12月, 2015 5 次提交
  15. 27 10月, 2015 1 次提交
  17. 10 9月, 2015 2 次提交
    • W
      watchdog: add a driver to support SAMA5D4 watchdog timer · 76534860
      由 Wenyou Yang 提交于 
      From SAMA5D4, the watchdog timer is upgrated with a new feature,
which is describled as in the datasheet, "WDT_MR can be written
until a LOCKMR command is issued in WDT_CR".
That is to say, as long as the bootstrap and u-boot don't issue
a LOCKMR command, WDT_MR can be written more than once in the driver.

So the SAMA5D4 watchdog driver's implementation is different from
the at91sam9260 watchdog driver implemented in file at91sam9_wdt.c.
The user application open the device file to enable the watchdog timer
hardware, and close to disable it, and set the watchdog timer timeout
by seting WDV and WDD fields of WDT_MR register, and ping the watchdog
by issuing WDRSTT command to WDT_CR register with hard-coded key.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      76534860
    • A
      watchdog: NXP LPC18xx Watchdog Timer Driver · 7c25f8c9
      由 Ariel D'Alessandro 提交于 
      This commit adds support for the watchdog timer found in NXP LPC SoCs
family, which includes LPC18xx/LPC43xx. Other SoCs in that family may
share the same watchdog hardware.

Watchdog driver registers a restart handler that will restart the system
by performing an incorrect feed after ensuring the watchdog is enabled in
reset mode.

As watchdog cannot be disabled in hardware, driver's stop routine will
regularly send a keepalive ping using a timer.
Signed-off-by: NAriel D'Alessandro <ariel@vanguardiasur.com.ar>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      7c25f8c9
  19. 22 6月, 2015 3 次提交
  21. 30 4月, 2015 1 次提交
  23. 18 2月, 2015 2 次提交
  25. 21 10月, 2014 5 次提交
  27. 24 9月, 2014 1 次提交
  29. 11 6月, 2014 2 次提交
  31. 10 6月, 2014 1 次提交
  33. 31 3月, 2014 1 次提交
  35. 29 1月, 2014 2 次提交
  37. 18 11月, 2013 3 次提交
  39. 17 9月, 2013 1 次提交
  41. 11 9月, 2013 1 次提交
  43. 12 7月, 2013 2 次提交