PCI: add descriptions for missing function parameters.
Eliminate all kernel-doc warnings here.
Signed-off-by: NRandy Dunlap <rdunlap@xenotime.net>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

I believe the change that broke things is introduction of
pci_fixup_parent_subordinate_busnr().

The patch here does two things:
- hunk #1 should fix the problems you've seen when you boot without
  additional "pci" kernel options;
- hunk #2 supposedly fixes boot with "pci=assign-busses" option which
  otherwise hangs Acer TM81xx machines as reported.

Please try this with and without "pci=assign-busses". If it boots,
I'd like to see 'lspci -vvx' for both cases.
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

This function expects an unsigned 32-bit type as its third argument:

 static u32 pci_size(u32 base, u32 maxbase, u32 mask)

However, given these definitions:

 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)

these two calls in drivers/pci/probe.c are problematic for architectures
for which a UL is not equivalent to a u32:

 sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
 sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);

Hence the below compile warning when building for ARCH=ppc64:

 drivers/pci/probe.c: In function `pci_read_bases':
 /.../probe.c:168: warning: large integer implicitly truncated to unsigned type
 /.../probe.c:218: warning: large integer implicitly truncated to unsigned type

Here is a simple fix.
Signed-off-by: NAmos Waterland <apw@us.ibm.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

pcibus_to_cpumask expands into more than just an initialiser so gcc
moans about code before variable declarations.
Signed-off-by: NAlan Cox <alan@redhat.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

This patch makes some small rearrangements of the PCI probing code in
order to make it possible for arch code to set up the PCI tree
without needing to duplicate code from the PCI layer unnecessarily.
PPC64 will use this to set up the PCI tree from the Open Firmware
device tree, which we need to do on logically-partitioned pSeries
systems.
Signed-off-by: NPaul Mackerras <paulus@samba.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

- support PCI PM CAP version 3 (as defined in PCI PM Interface Spec v1.2)

- pci/probe.c sets the PM state initially to 4 which is D3cold.  add a
  PCI_UNKNOWN

- minor cleanups
Signed-off-by: NDaniel Ritz <daniel.ritz@gmx.ch>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

This patch removes CONFIG_PCI_NAMES.
Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

The setup-bus code doesn't work correctly for configurations
with more than one display adapter in the same PCI domain.
This stuff actually is a leftover of an early 2.4 PCI setup code
and apparently it stopped working after some "bridge_ctl" changes.
So the best thing we can do is just to remove it and rely on the fact
that any firmware *has* to configure VGA port forwarding for the boot
display device properly.

But then we need to ensure that the bus->bridge_ctl will always
contain valid information collected at the probe time, therefore
the following change in pci_scan_bridge() is needed.
Signed-off-by: NIvan Kokshaysky <ink@jurassic.park.msu.ru>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

With the number of PCI bus resources increased to 8, we can
handle the subtractive decode PCI-PCI bridge like a normal
bridge, taking into account standard PCI-PCI bridge windows
(resources 0-2). This helps to avoid problems with peer-to-peer DMA
behind such bridges, poor performance for MMIO ranges outside bridge
windows and prefetchable vs. non-prefetchable memory issues.

To reflect the fact that such bridges do forward all addresses to
the secondary bus (transparency), remaining bus resources 3-7 are
linked to resources 0-4 of the primary bus. These resources will be
used as fallback by resource management code if allocation from
standard bridge windows fails for some reason.
Signed-off-by: NIvan Kokshaysky <ink@jurassic.park.msu.ru>
Acked-by: NDominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

When the cardbus bridge is behind another bridge change the routing
in the parent bridge for new cards.  This fixes Cardbus on various AMD64
laptops.
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

When a pci child bus is created, add it to the parent's children list
immediately rather than waiting till pci_bus_add_devices().  For hot-plug
bridges/devices, pci_bus_add_devices() may be called much later, after they
have been properly configured.  In the meantime, this allows us to use the
normal pci bus search functions for the hot-plug bridges/buses.
Signed-off-by: NRajesh Shah <rajesh.shah@intel.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

With root bridge and pci bridge hot-plug, new buses and devices can be added
or removed at run time.  Protect the pci bus and device lists with the pci
lock when doing so.
Signed-off-by: NRajesh Shah <rajesh.shah@intel.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

When hot-plugging a root bridge, as we try to assign bus numbers we may find
that the hotplugged hieratchy has more PCI to PCI bridges (i.e.  bus
requirements) than available.  Make sure we don't step over an existing bus
when that happens.
Signed-off-by: NRajesh Shah <rajesh.shah@intel.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

When you hot-plug a (root) bridge hierarchy, it may have p2p bridges and
devices attached to it that have not been configured by firmware.  In this
case, we need to configure the devices before starting them.  This patch
separates device start from device scan so that we can introduce the
configuration step in the middle.

I kept the existing semantics for pci_scan_bus() since there are a huge number
of callers to that function.

Also, I have no way of testing the changes I made to the parisc files, so this
needs review by those folks.  Sorry for the massive cross-post, this touches
files in many different places.
Signed-off-by: NRajesh Shah <rajesh.shah@intel.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

On 64-bit machines, PCI_BASE_ADDRESS_MEM_MASK and other mask constants
passed to pci_size() are 64-bit (for example ~0x0fUL).  However, pci_size
does comparisons between the u32 arguments and the mask, which will fail
even though any result from pci_size is still just 32-bit.

Changing the mask argument to u32 seems the obvious thing to do, since all
arithmetic in the function is 32-bit and having a larger mask makes no
sense.

This triggered on a PPC64 system here where an adapter (VGA, as it
happened) had a memory region base of 0xfe000000 and a sz of the same,
matching the if (max == maxbase ...) test at the bottom of pci_size but
failing the mask comparison.  Quite a corner case which I guess explains
why we haven't seen it until now.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Acked-by: NGreg KH <greg@kroah.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!