eerd and eewr don't exist on pre PCIe devices
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NDon Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

A large whitespace change to e1000_hw.[ch] in order to update it to kernel coding
style (by running lindent).  Updated function header comments into kdoc style.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NDon Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

e1000 was using one particular way to detect link, but with the advent
of some of the newer hardware designs using SERDES connections, tests
for link must completely cover all cases.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NDon Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

after removal of pcie, need to remove some unnecessary functions
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NDon Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

this patch is the first in a series of clean up patches for e1000 to drop
unused code, and update the driver to kernel spec, and then, to update the
driver to have all available bug fixes.

Call it the e1000 weight loss plan.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NDon Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

when testing the jumbo frames with pages patch, the stats would
show rx_missed errors (dropped packets) even when connected to a
link partner with flow control enabled.

this indicates that for this MTU (9000) the flow control
thresholds are not adjusting correctly.

In fact, before this change, the FCRTH (xoff threshold) is 36864
when the fifo size is only 40000, with 9000 byte MTU.

fix it so that we at least have room for one frame after we send
the xoff.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Conglomerate from 4 separate patches from Joe.
Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

On Thu, 2008-03-06 at 10:07 -0800, Kok, Auke wrote:
> send me a patch for e1000 and for ixgb and I'll happily apply those :)

boolean_t to bool
TRUE to true
FALSE to false
comment typo ahread to ahead
Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

These driver changes incorporate the proposed PCI-X / PCI-Express read byte
count interface.  Reading and setting those valuse doesn't take place
"manually", instead wrapping functions are called to allow quirks for some
PCI bridges.

Signed-off by: Peter Oruba <peter.oruba@amd.com>
Based on work by Stephen Hemminger <shemminger@linux-foundation.org>
Acked-by: NAuke Kok <auke-jan.h.kok@intel.com>
Cc: Jeff Garzik <jeff@garzik.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This blade-specific board form factor is identical to the 82571EB
board.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This patch adds support for 2 new board variants:
- A Quad port fiber 82571 board
- A blade version of the 82571 quad copper board
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Correct mis-spellings of "algorithm", "appear", "consistent" and
(shame, shame) "kernel".
Signed-off-by: NRobert P. J. Day <rpjday@mindspring.com>
Signed-off-by: NAdrian Bunk <bunk@stusta.de>

Add 3 extra packet redirect counters for tracking purposes to make sure
we can test that all packets arrive properly.

Originally from Jesse Brandeburg <jesse.brandeburg@intel.com>,
rewritten to use feature flags by me.
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Assign the PBA to be large enough to contain at least 2 jumbo frames on
all adapters. This dramatically increases performance on several adapters
and fixes TX performance degradation issues where the PBA was misallocated
in the old algorithm.
Signed-off-by: NBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NArjan van de Ven <arjan@linux.intel.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

In rare occasions, ESB2 systems would end up started without the RX
unit being turned on. Add a check that runs post-init to work around
this issue.

Originally from Jesse Brandeburg <jesse.brandeburg@intel.com>,
rewritten to use feature flags by me.
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Several bugs existed in how we handle manageability issues all
over the driver.  This patch consolidates all the managability
release and init code in two single functions and call them from
appropriate locations. This fixes several BMC packet redirect issues
and powerup/down hiccups.

Originally from Jesse Brandeburg <jesse.brandeburg@intel.com>, rewritten
to use feature flags by me.
Signed-off-by: NJeff Garzik <jeff@garzik.org>

The 82543 chip does not count tx_carrier_errors properly in FD mode;
report zeros instead of garbage.

Originally from Jesse Brandeburg <jesse.brandeburg@intel.com>, rewritten
to use feature flags by me.
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Makes future changes a bit more readable.
Signed-off-by: NJeff Garzik <jeff@garzik.org>

ICH8 will soon be followed by newer chipsets bearing the same acronym,
thus we remove the '8' and make it independent of the version number in
the platform name.
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Add support for a Low Profile quad-port PCI-E adapter and 2 variants
of the ICH8 systems' onboard NIC's.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Order pci-e capability struct according to bus/pci bus width ordering
preserving the hard pci spec numbers.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

On ich systems during PHY power down to D3, the voltage regulators
were left on.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Small whitespace changes, comment changes, typo fixes.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Threshold bitmasks for prefetch, host and writeback were clearing
bits that they were not supposed to. The leftmost 2 bits in the byte
for each threshold are reserved.
Signed-off-by: NBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Several minor issues exist in the low-level device handling code of
e1000. The NVM and EEPROM writing/reading code was updated which fixes
unneeded delays, adds proper eeprom aqcuiring steps and handle shadow
ram and flash access. Minor cosmetic adjustments to the polarity code
adding symbols. PHY reset code mistakenly distinguished between MAC
types instead of PHY types, and was fixes.
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Manageability is using one more RAR entry than we anticipated earlier
for ICH8.
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Add code to display the detected PCI-E bus width.
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Several hardware bits were set all over the driver and have been
consolidated into a single function.
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Add 4 multicast and broadcast hardware counters (rx/tx), and eliminate
as many non-hardware counters as possible.
Signed-off-by: NMitch Williams <mitch.a.williams@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Signed-off-by: NNicholas Nunley <nicholas.d.nunley@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Sogned-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

This update to the copyright header adds the mailinglist, and aligns it
with the kernel licensing as well as remove the offending 'all rights
reserved'.
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

Device 0x10a4 is a double 82571 on a single PCI-Express card and
has 4 gigabit capable ports.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

- make needlessly global functions static
- #if 0 the following unused global functions:
  - e1000_hw.c: e1000_mc_addr_list_update()
  - e1000_hw.c: e1000_read_reg_io()
  - e1000_hw.c: e1000_enable_pciex_master()
  - e1000_hw.c: e1000_ife_disable_dynamic_power_down()
  - e1000_hw.c: e1000_ife_enable_dynamic_power_down()
  - e1000_hw.c: e1000_write_ich8_word()
  - e1000_hw.c: e1000_duplex_reversal()
  - e1000_main.c: e1000_io_read()
Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Cc: John Ronciak <john.ronciak@intel.com>
Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
Cc: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Cc: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NJeff Garzik <jeff@garzik.org>

This implements the core new functions needed for ich8's internal
NIC. This includes:

* ich8 specific read/write code
* flash/nvm access code
* software semaphore flag functions
* 10/100 PHY (fe - no gigabit speed) support for low-end versions
* A workaround for a powerdown sequence problem discovered that
affects a small number of motherboard.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>

M88 rev 2 PHY needs a longer downshift to function properly. This adds
a much longer downshift counter for this specific device.
Signed-off-by: NJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: NAuke Kok <auke-jan.h.kok@intel.com>