1. 11 11月, 2016 1 次提交
    • M
      drm/amdgpu: Attach exclusive fence to prime exported bo's. (v5) · 8e94a46c
      Mario Kleiner 提交于
      External clients which import our bo's wait only
      for exclusive dmabuf-fences, not on shared ones,
      ditto for bo's which we import from external
      providers and write to.
      
      Therefore attach exclusive fences on prime shared buffers
      if our exported buffer gets imported by an external
      client, or if we import a buffer from an external
      exporter.
      
      See discussion in thread:
      https://lists.freedesktop.org/archives/dri-devel/2016-October/122370.html
      
      Prime export tested on Intel iGPU + AMD Tonga dGPU as
      DRI3/Present Prime render offload, and with the Tonga
      standalone as primary gpu.
      
      v2: Add a wait for all shared fences before prime export,
          as suggested by Christian Koenig.
      
      v3: - Mark buffer prime_exported in amdgpu_gem_prime_pin,
          so we only use the exclusive fence when exporting a
          bo to external clients like a separate iGPU, but not
          when exporting/importing from/to ourselves as part of
          regular DRI3 fd passing.
      
          - Propagate failure of reservation_object_wait_rcu back
          to caller.
      
      v4: - Switch to a prime_shared_count counter instead of a
            flag, which gets in/decremented on prime_pin/unpin, so
            we can switch back to shared fences if all clients
            detach from our exported bo.
      
          - Also switch to exclusive fence for prime imported bo's.
      
      v5: - Drop lret, instead use int ret -> long ret, as proposed
            by Christian.
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95472
      Tested-by: Mike Lothian <mike@fireburn.co.uk> (v1)
      Signed-off-by: NMario Kleiner <mario.kleiner.de@gmail.com>
      Reviewed-by: Christian König <christian.koenig@amd.com>.
      Cc: Christian König <christian.koenig@amd.com>
      Cc: Michel Dänzer <michel.daenzer@amd.com>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      Cc: stable@vger.kernel.org
      8e94a46c
  2. 08 11月, 2016 1 次提交
  3. 01 11月, 2016 3 次提交
  4. 31 10月, 2016 1 次提交
  5. 29 10月, 2016 2 次提交
  6. 28 10月, 2016 1 次提交
  7. 27 10月, 2016 1 次提交
  8. 26 10月, 2016 2 次提交
  9. 25 10月, 2016 4 次提交
  10. 21 10月, 2016 6 次提交
  11. 19 10月, 2016 1 次提交
  12. 14 10月, 2016 6 次提交
  13. 13 10月, 2016 5 次提交
  14. 07 10月, 2016 4 次提交
  15. 04 10月, 2016 2 次提交