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  1. 18 12月, 2007 1 次提交
    • T
      sata_sil: fix spurious IRQ handling · 8cf32ac6
      由 Tejun Heo 提交于 
      Interestingly, sata_sil raises spurious interrupts if it's coupled
with Sil SATA_PATA bridge.  Currently, sata_sil interrupt handler is
strict about spurious interrupts and freezes the port when it occurs.
This patch makes it more forgiving.

* On SATA PHY event interrupt, serror value is checked to see whether
  it really is PHYRDY CHG event.  If not, SATA PHY event interrupt is
  ignored.

* If ATA interrupt occurs while no command is in progress, it's
  cleared and ignored.

This fixes bugzilla bug 9505.

  http://bugzilla.kernel.org/show_bug.cgi?id=9505Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      8cf32ac6
  3. 08 12月, 2007 4 次提交
    • T
      libata: kill spurious NCQ completion detection · 459ad688
      由 Tejun Heo 提交于 
      Spurious NCQ completion detection implemented in ahci was incorrect.
On AHCI receving and processing FISes and raising interrupts are not
interlocked and spurious interrupts are expected.

For example, if an interrupt occurs while interrupt handler is running
and the running interrupt handler handles the event the new IRQ
indicated, after IRQ handler finishes, it will be executed again
because IRQ pending bit is set by the new interrupt but there won't be
anything to process.

Please read the following message for more information.

  http://article.gmane.org/gmane.linux.ide/26012

This patch...

* Removes all spurious IRQ whining from ahci.  Spurious NCQ completion
  detection was completely wrong.  Spurious D2H Register FIS taught us
  that some early drives send spurious D2H Register FIS with I bit set
  while NCQ commands are in progress but none of recent drives does
  that and even the ones which show such behavior can do NCQ fine.

* Kills all NCQ blacklist entries which were added because of spurious
  NCQ completions.  I tracked down each commit and verified all
  removed ones are actually added because of spurious completions.

  WD740ADFD-00NLR1 wasn't deleted but moved upward because the drive
  not only had spurious NCQ completions but also is slow on sequential
  data transfers if NCQ is enabled.

  Maxtor 7V300F0 was added by 0e3dbc01
  from Alan Cox.  I can only find evidences that the drive only had
  troubles with spuruious completions by searching the mailing list.
  This entry needs to be verified and removed if it doesn't have other
  NCQ related problems.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      459ad688
    • T
      ahci: don't attach if ICH6 is in combined mode · c4f7792c
      由 Tejun Heo 提交于 
      ICH6 R/Ms share PCI ID between piix and ahci modes and we've been
allowing ahci to attach regardless of how BIOS configured it.
However, enabling AHCI mode when the controller is in combined mode
can result in unexpected behavior.  Don't attach if the controller is
in combined mode.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Bill Nottingham <notting@redhat.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      c4f7792c
    • P
      ata_piix: add Toshiba Tecra M4 to broken suspend list · d1aa690a
      由 Peter Schwenke 提交于 
      Add Toshiba Tecra M4 to broken suspend list.  This is from OSDL
bugzilla bug 7780.
Signed-off-by: NPeter Schwenke <peter@bluetoad.com.au>
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      d1aa690a
    • T
      ahci: fix engine reset failed message · 994056d7
      由 Tejun Heo 提交于 
      There isn't much point in reporting -EOPNOTSUPP as failure.  Also the
message was missing newline.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      994056d7
  5. 05 12月, 2007 4 次提交
  7. 02 12月, 2007 8 次提交
  9. 27 11月, 2007 2 次提交
    • T
      libata: bump transfer chunk size if it's odd · e190222d
      由 Tejun Heo 提交于 
      None of the drives I have follows what the standard says about
transfer chunk size.  Of the four SATA and six PATA ATAPI devices
tested, four ignore transfer chunk size completely and the ones which
honor it don't behave according to the spec when it's odd.

According to the spec, transfer chunk size can be odd if the amount of
data to transfer equals or is smaller than the chunk size and the
device can indicate the same odd number and transfer the whole thing
at one go with a pad byte appended.  However, in reality, none of the
drives I have does that.  They all indicate and transfer even number
of bytes one byte shorter than the chunk size first; then indicate and
transfer two bytes, which is clearly out of spec.

In addition to unnecessary second PIO data phase, this also creates a
weird problem when combined with SATA controllers which perform PIO
via DMA.  Some of these controllers use actualy number of bytes
received to update DMA pointer so chunks which are sized 4n + 2 makes
DMA pointer off by two bytes.  This causes data corruption and buffer
overruns.

This patch rounds nbytes up to the nearest even number such that ATAPI
devices don't split data transfer for the last odd byte.  This
shouldn't confuse controllers which depend on transfer chunk size as
devices will report the rounded-up number, actually transfer that much
and padding buffer is there to receive them.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      e190222d
    • S
      libata: Return proper ATA INT status in pata_bf54x driver · dc86f6d4
      由 sonic zhang 提交于 
      INT status can be OR.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      dc86f6d4
  11. 24 11月, 2007 10 次提交
  13. 19 11月, 2007 9 次提交
  15. 10 11月, 2007 1 次提交
  17. 09 11月, 2007 1 次提交
    • T
      libata: port and host should be stopped before hardware resources are released · 32ebbc0c
      由 Tejun Heo 提交于 
      Port / host stop calls used to be made from ata_host_release() which
is called after all hardware resources acquired after host allocation
are released.  This is wrong as port and host stop routines often
access the hardware.

Add separate devres for port / host stop which is invoked right after
IRQ is released but with all other hardware resources intact.  The
devres is added iff ->host_stop and/or ->port_stop exist.

This problem has been spotted by Mark Lord.
Signed-off-by: NTejun Heo <htejun@gmail.com>
Cc: Mark Lord <liml@rtr.ca>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      32ebbc0c