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  1. 28 3月, 2016 2 次提交
  3. 02 3月, 2016 1 次提交
  5. 21 2月, 2016 1 次提交
  7. 10 2月, 2016 3 次提交
  9. 04 2月, 2016 2 次提交
    • J
      spi: pxa2xx: Fix too early chipselect deassert · 7a8d44bc
      由 Jarkko Nikula 提交于 
      There is a chance that chipselect is deasserted too early while the last
clock cycle is still running. Protocol analyzers will see this as a failed
last byte. This is more likely to occur with slow bitrates, for instance
at 25 kbps.

Reason for this is when using SPI mode 0 that both SPI host controller and
SPI slave will drive the data lines at the falling edge of clock signal
and sample at the rising edge. Receive FIFO gets the last bit now at the
rising edge and code sees transfer to be finished either by the interrupt
in PIO mode or by the DMA completion in DMA mode.

The SSP Time Out register SSTO should take care of delaying the
completion but it does not seems to have effect at least on Intel
Skylake and Broxton even when using long enough values. Depending on
timing code may get into point where chipselect is deasserted while the
last clock cycle is still running at its second half cycle.

Fix this by adding a wait loop in giveback() that waits until SSP becomes
idle before deasserting the chipselect.
Reported-by: NWeifeng Voon <weifeng.voon@intel.com>
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      7a8d44bc
    • J
      spi: pxa2xx: Update comment in int_transfer_complete() · 07550df0
      由 Jarkko Nikula 提交于 
      The register writes here actually don't stop the SSP but clean and
disable interrupts and set the receive FIFO inactivity timeout to zero.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      07550df0
  11. 27 1月, 2016 1 次提交
  13. 21 11月, 2015 1 次提交
  15. 30 10月, 2015 5 次提交
  17. 23 10月, 2015 5 次提交
  19. 17 10月, 2015 1 次提交
  21. 02 10月, 2015 1 次提交
  23. 26 9月, 2015 2 次提交
  25. 18 9月, 2015 3 次提交
  27. 02 9月, 2015 1 次提交
    • T
      spi: spi-pxa2xx: Check status register to determine if SSSR_TINT is disabled · 02bc933e
      由 Tan, Jui Nee 提交于 
      On Intel Baytrail, there is case when interrupt handler get called, no SPI
message is captured. The RX FIFO is indeed empty when RX timeout pending
interrupt (SSSR_TINT) happens.

Use the BIOS version where both HSUART and SPI are on the same IRQ. Both
drivers are using IRQF_SHARED when calling the request_irq function. When
running two separate and independent SPI and HSUART application that
generate data traffic on both components, user will see messages like
below on the console:

  pxa2xx-spi pxa2xx-spi.0: bad message state in interrupt handler

This commit will fix this by first checking Receiver Time-out Interrupt,
if it is disabled, ignore the request and return without servicing.
Signed-off-by: NTan, Jui Nee <jui.nee.tan@intel.com>
Acked-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
      02bc933e
  29. 05 8月, 2015 2 次提交
  31. 04 8月, 2015 1 次提交
  33. 01 8月, 2015 1 次提交
    • J
      spi: pxa2xx: Add support for Intel Sunrisepoint · 34cadd9c
      由 Jarkko Nikula 提交于 
      Major difference in LPSS SPI between Intel Sunrisepoint PCH and earlier
platforms is an integrated DMA (iDMA) engine. iDMA is an IP that is private
for each LPSS host controller (UART/SPI/I2C). Other differences are private
register space offset, a few private registers that are in different
location and FIFO thresholds.

Intel Sunrisepoint LPSS SPI and iDMA devices are probed and registered in
MFD layer as platform devices. Here these compound devices are detected by
matching against known PCI IDs. This allows us to share
pxa2xx_spi_acpi_get_pdata() for setting up the platform data instead of
duplicating it in MFD part.

This patch adds configuration for Intel Sunrisepoint LPSS SPI, above
detection and DMA filter function that picks the DMA channel only from an
associated iDMA block.
Signed-off-by: NJarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      34cadd9c
  35. 15 6月, 2015 1 次提交
  37. 05 6月, 2015 3 次提交
  39. 31 3月, 2015 1 次提交
  41. 25 3月, 2015 2 次提交