1. 14 4月, 2020 1 次提交
  2. 06 3月, 2020 2 次提交
  3. 04 3月, 2020 1 次提交
  4. 24 2月, 2020 1 次提交
  5. 11 12月, 2019 1 次提交
  6. 13 8月, 2019 1 次提交
    • G
      drm/i915/gvt: no need to check return value of debugfs_create functions · f8871ec8
      Greg Kroah-Hartman 提交于
      When calling debugfs functions, there is no need to ever check the
      return value.  The function can work or not, but the code logic should
      never do something different based on this.
      
      Because there is no need to check these functions, a number of local
      functions can be made to return void to simplify things as nothing can
      fail.
      
      Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
      Cc: Zhi Wang <zhi.a.wang@intel.com>
      Cc: Jani Nikula <jani.nikula@linux.intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Cc: David Airlie <airlied@linux.ie>
      Cc: Daniel Vetter <daniel@ffwll.ch>
      Cc: intel-gvt-dev@lists.freedesktop.org
      Cc: intel-gfx@lists.freedesktop.org
      Cc: dri-devel@lists.freedesktop.org
      Reviewed-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      f8871ec8
  7. 31 1月, 2019 1 次提交
  8. 02 1月, 2019 1 次提交
    • Z
      drm/i915/gvt: Change KVMGT as self load module · 9bdb0734
      Zhenyu Wang 提交于
      This trys to make 'kvmgt' module as self loadable instead of loading
      by i915/gvt device model. So hypervisor specific module could be
      stand-alone, e.g only after loading hypervisor specific module, GVT
      feature could be enabled via specific hypervisor interface, e.g VFIO/mdev.
      
      So this trys to use hypervisor module register/unregister interface
      for that. Hypervisor module needs to take care of module reference
      itself when working for hypervisor interface, e.g for VFIO/mdev,
      hypervisor module would reference counting mdev when open and release.
      
      This makes 'kvmgt' module really split from GVT device model. User
      needs to load 'kvmgt' to enable VFIO/mdev interface.
      
      v6:
      - remove unused variable
      
      v5:
      - put module reference in register error path
      
      v4:
      - fix checkpatch warning
      
      v3:
      - Fix module reference handling for device open and release. Unused
        mdev devices would be cleaned up in device unregister when module unload.
      
      v2:
      - Fix kvmgt order after i915 for built-in case
      
      Cc: "Yuan, Hang" <hang.yuan@intel.com>
      Cc: Alex Williamson <alex.williamson@redhat.com>
      Cc: "He, Min" <min.he@intel.com>
      Reviewed-by: NYuan, Hang <hang.yuan@intel.com>
      Acked-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      9bdb0734
  9. 10 12月, 2018 1 次提交
  10. 07 12月, 2018 1 次提交
  11. 14 8月, 2018 1 次提交
    • H
      drm/i915/gvt: fix cleanup sequence in intel_gvt_clean_device · 3fd34ac0
      Hang Yuan 提交于
      Create one vGPU and then unbind IGD device from i915 driver. The following
      oops will happen. This patch will free vgpu resource first and then gvt
      resource to remove these oops.
      
      BUG: unable to handle kernel NULL pointer dereference at       00000000000000a8
        PGD 80000003c9d2c067 P4D 80000003c9d2c067 PUD 3c817c067 P      MD 0
        Oops: 0002 [#1] SMP PTI
        RIP: 0010:down_write+0x1b/0x40
      Call Trace:
        debugfs_remove_recursive+0x46/0x1a0
        intel_gvt_debugfs_remove_vgpu+0x15/0x30 [i915]
        intel_gvt_destroy_vgpu+0x2d/0xf0 [i915]
        intel_vgpu_remove+0x2c/0x30 [kvmgt]
        mdev_device_remove_ops+0x23/0x50 [mdev]
        mdev_device_remove+0xdb/0x190 [mdev]
        mdev_device_remove+0x190/0x190 [mdev]
        device_for_each_child+0x47/0x90
        mdev_unregister_device+0xd5/0x120 [mdev]
        intel_gvt_clean_device+0x91/0x120 [i915]
        i915_driver_unload+0x9d/0x120 [i915]
        i915_pci_remove+0x15/0x20 [i915]
        pci_device_remove+0x3b/0xc0
        device_release_driver_internal+0x157/0x230
        unbind_store+0xfc/0x150
        kernfs_fop_write+0x10f/0x180
        __vfs_write+0x36/0x180
        ? common_file_perm+0x41/0x130
        ? _cond_resched+0x16/0x40
        vfs_write+0xb3/0x1a0
        ksys_write+0x52/0xc0
        do_syscall_64+0x55/0x100
        entry_SYSCALL_64_after_hwframe+0x44/0xa9
      
      BUG: unable to handle kernel NULL pointer dereference at 0      000000000000038
        PGD 8000000405bce067 P4D 8000000405bce067 PUD 405bcd067 PM      D 0
        Oops: 0000 [#1] SMP PTI
        RIP: 0010:hrtimer_active+0x5/0x40
      Call Trace:
        hrtimer_try_to_cancel+0x25/0x120
        ? tbs_sched_clean_vgpu+0x1f/0x50 [i915]
        hrtimer_cancel+0x15/0x20
        intel_gvt_destroy_vgpu+0x4c/0xf0 [i915]
        intel_vgpu_remove+0x2c/0x30 [kvmgt]
        mdev_device_remove_ops+0x23/0x50 [mdev]
        mdev_device_remove+0xdb/0x190 [mdev]
        ? mdev_device_remove+0x190/0x190 [mdev]
        device_for_each_child+0x47/0x90
        mdev_unregister_device+0xd5/0x120 [mdev]
        intel_gvt_clean_device+0x89/0x120 [i915]
        i915_driver_unload+0x9d/0x120 [i915]
        i915_pci_remove+0x15/0x20 [i915]
        pci_device_remove+0x3b/0xc0
        device_release_driver_internal+0x157/0x230
        unbind_store+0xfc/0x150
        kernfs_fop_write+0x10f/0x180
        __vfs_write+0x36/0x180
        ? common_file_perm+0x41/0x130
        ? _cond_resched+0x16/0x40
        vfs_write+0xb3/0x1a0
        ksys_write+0x52/0xc0
        do_syscall_64+0x55/0x100
        entry_SYSCALL_64_after_hwframe+0x44/0xa9
      
      Fixes: bc7b0be3("drm/i915/gvt: Add basic debugfs infrastructure")
      Fixes: afe04fbe("drm/i915/gvt: create an idle vGPU")
      Signed-off-by: NHang Yuan <hang.yuan@linux.intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      3fd34ac0
  12. 13 8月, 2018 1 次提交
  13. 07 8月, 2018 1 次提交
  14. 10 7月, 2018 1 次提交
  15. 13 6月, 2018 1 次提交
  16. 18 5月, 2018 2 次提交
    • C
      drm/i915/gvt: Use sched_lock to protect gvt scheduler logic. · 9a512e23
      Colin Xu 提交于
      The scheduler lock(gvt->sched_lock) is used to protect gvt
      scheduler logic, including the gvt scheduler structure(gvt->scheduler
      and per vgpu schedule data(vgpu->sched_data, vgpu->sched_ctl).
      
      v9:
        - Change commit author since the patches are improved a lot compared
          with original version.
          Original author: Pei Zhang <pei.zhang@intel.com>
        - Rebase to latest gvt-staging.
      v8:
        - Correct coding wqstyle.
        - Rebase to latest gvt-staging.
      v7:
        - Remove gtt_lock since already proteced by gvt_lock and vgpu_lock.
      v6:
        - Rebase to latest gvt-staging.
      v5:
        - Rebase to latest gvt-staging.
      v4:
        - Rebase to latest gvt-staging.
      v3: update to latest code base
      Signed-off-by: NPei Zhang <pei.zhang@intel.com>
      Signed-off-by: NColin Xu <colin.xu@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      9a512e23
    • C
      drm/i915/gvt: Use vgpu_lock to protect per vgpu access · f25a49ab
      Colin Xu 提交于
      The patch set splits out 2 small locks from the original big gvt lock:
        - vgpu_lock protects per-vGPU data and logic, especially the vGPU
          trap emulation path.
        - sched_lock protects gvt scheudler structure, context schedule logic
          and vGPU's schedule data.
      
      Use vgpu_lock to replace the gvt big lock. By doing this, the
      mmio read/write trap path, vgpu virtual event emulation and other
      vgpu related process, would be protected under per vgpu_lock.
      
      v9:
        - Change commit author since the patches are improved a lot compared
          with original version.
          Original author: Pei Zhang <pei.zhang@intel.com>
        - Rebase to latest gvt-staging.
      v8:
        - Correct coding and comment style.
        - Rebase to latest gvt-staging.
      v7:
        - Remove gtt_lock since already proteced by gvt_lock and vgpu_lock.
        - Fix a typo in intel_gvt_deactivate_vgpu, unlock the wrong lock.
      v6:
        - Rebase to latest gvt-staging.
      v5:
        - Rebase to latest gvt-staging.
        - intel_vgpu_page_track_handler should use vgpu_lock.
      v4:
        - Rebase to latest gvt-staging.
        - Protect vgpu->active access with vgpu_lock.
        - Do not wait gpu idle in vgpu_lock.
      v3: update to latest code base
      v2: add gvt->lock in function gvt_check_vblank_emulation
      
      Performance comparison on Kabylake platform.
        - Configuration:
          Host: Ubuntu 16.04.
          Guest 1 & 2: Ubuntu 16.04.
      
      glmark2 score comparison:
        - Configuration:
          Host: glxgears.
          Guests: glmark2.
      +--------------------------------+-----------------+
      | Setup                          | glmark2 score   |
      +--------------------------------+-----------------+
      | unified lock, iommu=on         | 58~62 (avg. 60) |
      +--------------------------------+-----------------+
      | unified lock, iommu=igfx_off   | 57~61 (avg. 59) |
      +--------------------------------+-----------------+
      | per-logic lock, iommu=on       | 60~68 (avg. 64) |
      +--------------------------------+-----------------+
      | per-logic lock, iommu=igfx_off | 61~67 (avg. 64) |
      +--------------------------------+-----------------+
      
      lock_stat comparison:
        - Configuration:
          Stop lock stat immediately after boot up.
          Boot 2 VM Guests.
          Run glmark2 in guests.
          Start perf lock_stat for 20 seconds and stop again.
        - Legend: c - contentions; w - waittime-avg
      +------------+-----------------+-----------+---------------+------------+
      |            | gvt_lock        |sched_lock | vgpu_lock     | gtt_lock   |
      + lock type; +-----------------+-----------+---------------+------------+
      | iommu set  | c     | w       | c  | w    | c    | w      | c   | w    |
      +------------+-------+---------+----+------+------+--------+-----+------+
      | unified;   | 20697 | 839     |N/A | N/A  | N/A  | N/A    | N/A | N/A  |
      | on         |       |         |    |      |      |        |     |      |
      +------------+-------+---------+----+------+------+--------+-----+------+
      | unified;   | 21838 | 658.15  |N/A | N/A  | N/A  | N/A    | N/A | N/A  |
      | igfx_off   |       |         |    |      |      |        |     |      |
      +------------+-------+---------+----+------+------+--------+-----+------+
      | per-logic; | 1553  | 1599.96 |9458|429.97| 5846 | 274.33 | 0   | 0.00 |
      | on         |       |         |    |      |      |        |     |      |
      +------------+-------+---------+----+------+------+--------+-----+------+
      | per-logic; | 1911  | 1678.32 |8335|445.16| 5451 | 244.80 | 0   | 0.00 |
      | igfx_off   |       |         |    |      |      |        |     |      |
      +------------+-------+---------+----+------+------+--------+-----+------+
      Signed-off-by: NPei Zhang <pei.zhang@intel.com>
      Signed-off-by: NColin Xu <colin.xu@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      f25a49ab
  17. 06 3月, 2018 1 次提交
    • C
      drm/i915/gvt: Provide generic page_track infrastructure for write-protected page · e502a2af
      Changbin Du 提交于
      This patch provide generic page_track infrastructure for write-protected
      guest page. The old page_track logic gets rewrote and now stays in a new
      standalone page_track.c. This page track infrastructure can be both used
      by vGUC and GTT shadowing.
      
      The important change is that it uses radix tree instead of hash table.
      We don't have a predictable number of pages that will be tracked.
      
      Here is some performance data (duration in us) of looking up a element:
      Before: (aka. intel_vgpu_find_tracked_page)
       0.091 0.089 0.090 ... 0.093 0.091 0.087 ... 0.292 0.285 0.292 0.291
      After: (aka. intel_vgpu_find_page_track)
       0.104 0.105 0.100 0.102 0.102 0.100 ... 0.101 0.101 0.105 0.105
      
      The hash table has good performance at beginning, but turns bad with
      more pages being tracked even no 3D applications are running. As
      expected, radix tree has stable duration and very quick.
      
      The overall benchmark (tested with Heaven Benchmark) marginally improved
      since this is not the bottleneck. What we benefit more from this change
      is scalability.
      Signed-off-by: NChangbin Du <changbin.du@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      e502a2af
  18. 22 12月, 2017 1 次提交
  19. 08 12月, 2017 1 次提交
  20. 04 12月, 2017 1 次提交
    • T
      drm/i915/gvt: Dmabuf support for GVT-g · e546e281
      Tina Zhang 提交于
      This patch introduces a guest's framebuffer sharing mechanism based on
      dma-buf subsystem. With this sharing mechanism, guest's framebuffer can
      be shared between guest VM and host.
      
      v17:
      - modify VFIO_DEVICE_GET_GFX_DMABUF interface. (Alex)
      
      v16:
      - add x_hot and y_hot. (Gerd)
      - add flag validation for VFIO_DEVICE_GET_GFX_DMABUF. (Alex)
      - rebase 4.14.0-rc6.
      
      v15:
      - add VFIO_DEVICE_GET_GFX_DMABUF ABI. (Gerd)
      - add intel_vgpu_dmabuf_cleanup() to clean up the vGPU's dmabuf. (Gerd)
      
      v14:
      - add PROBE, DMABUF and REGION flags. (Alex)
      
      v12:
      - refine the lifecycle of dmabuf.
      
      v9:
      - remove dma-buf management. (Alex)
      - track the dma-buf create and release in kernel mode. (Gerd) (Daniel)
      
      v8:
      - refine the dma-buf ioctl definition.(Alex)
      - add a lock to protect the dmabuf list. (Alex)
      
      v7:
      - release dma-buf related allocations in dma-buf's associated release
        function. (Alex)
      - refine ioctl interface for querying plane info or create dma-buf.
        (Alex)
      
      v6:
      - align the dma-buf life cycle with the vfio device. (Alex)
      - add the dma-buf related operations in a separate patch. (Gerd)
      - i915 related changes. (Chris)
      
      v5:
      - fix bug while checking whether the gem obj is gvt's dma-buf when user
        change caching mode or domains. Add a helper function to do it.
        (Xiaoguang)
      - add definition for the query plane and create dma-buf. (Xiaoguang)
      
      v4:
      - fix bug while checking whether the gem obj is gvt's dma-buf when set
        caching mode or doamins. (Xiaoguang)
      
      v3:
      - declare a new flag I915_GEM_OBJECT_IS_GVT_DMABUF in drm_i915_gem_object
        to represent the gem obj for gvt's dma-buf. The tiling mode, caching
        mode and domains can not be changed for this kind of gem object. (Alex)
      - change dma-buf related information to be more generic. So other vendor
        can use the same interface. (Alex)
      
      v2:
      - create a management fd for dma-buf operations. (Alex)
      - alloc gem object's backing storage in gem obj's get_pages() callback.
        (Chris)
      Signed-off-by: NTina Zhang <tina.zhang@intel.com>
      Cc: Alex Williamson <alex.williamson@redhat.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Gerd Hoffmann <kraxel@redhat.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      e546e281
  21. 16 11月, 2017 3 次提交
  22. 08 9月, 2017 1 次提交
    • C
      drm/i915/gvt: Add support for PCIe extended configuration space · 02d578e5
      Changbin Du 提交于
      IGD is PCIe device and has extended configuration space. Checking
      the binary dump, we can see we have Caps located out of PCI compatible
      Configuration Space range.
      
      0x000: 86 80 12 19 17 04 10 00 06 00 00 03 00 00 00 00
      0x010: 04 00 00 10 08 00 00 00 0c 00 00 00 08 00 00 00
      0x020: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 b9 06
      0x030: 00 f8 ff ff 40 00 00 00 00 00 00 00 0b 01 00 00
      0x040: 09 70 0c 01 71 26 01 62 c8 00 04 84 00 00 00 00
      0x050: c1 00 00 00 39 00 00 00 00 00 00 00 01 00 00 a2
      0x060: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
      0x070: 10 ac 92 00 00 80 00 10 00 00 00 00 00 00 00 00
      0x080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
      0x090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
      0x0a0: 00 00 00 00 00 00 00 00 00 00 00 00 05 d0 01 00
      0x0b0: 18 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00
      0x0c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
      0x0d0: 01 00 22 00 00 80 00 00 00 00 00 00 00 00 00 00
      0x0e0: 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00
      0x0f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
      0x100: 1b 00 01 20 02 14 00 00 00 00 00 00 00 00 00 00
      ...
      
      Currently, we only emulate the PCI compatible Configuration Space.
      This is okay if we attach vGPU to PCI bus. But when we attach to
      a PCI Express bus (when Qemu emulates a Intel Q35 chipset which has
      PCIe slot), it will not work. Extended Configuration Space is required
      for a PCIe device.
      
      This patch extended the virtual configuration space from 256 bytes
      to 4KB bytes. So we are to be a *real* PCIe device. And for the
      Extended CapList we keep same to physical GPU.
      
      Cc: Laszlo Ersek <lersek@redhat.com>
      Tested-by: NLaszlo Ersek <lersek@redhat.com>
      Signed-off-by: NChangbin Du <changbin.du@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      02d578e5
  23. 08 6月, 2017 2 次提交
    • P
      drm/i915/gvt: Support event based scheduling · c713cb2f
      Ping Gao 提交于
      This patch decouple the time slice calculation and scheduler, let
      other event be able to trigger scheduling without impact the
      calculation for QoS.
      
      v2: add only one new enum definition.
      v3: fix typo.
      Signed-off-by: NPing Gao <ping.a.gao@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      c713cb2f
    • C
      drm/i915/gvt: implement per-vm mmio switching optimization · 0e86cc9c
      Changbin Du 提交于
      Commit ab9da627906a ("drm/i915: make context status notifier head be
      per engine") gives us a chance to inspect every single request. Then
      we can eliminate unnecessary mmio switching for same vGPU. We only
      need mmio switching for different VMs (including host).
      
      This patch introduced a new general API intel_gvt_switch_mmio() to
      replace the old intel_gvt_load/restore_render_mmio(). This function
      can be further optimized for vGPU to vGPU switching.
      
      To support individual ring switch, we track the owner who occupy
      each ring. When another VM or host request a ring we do the mmio
      context switching. Otherwise no need to switch the ring.
      
      This optimization is very useful if only one guest has plenty of
      workloads and the host is mostly idle. The best case is no mmio
      switching will happen.
      
      v2:
        o fix missing ring switch issue. (chuanxiao)
        o support individual ring switch.
      Signed-off-by: NChangbin Du <changbin.du@intel.com>
      Reviewed-by: NChuanxiao Dong <chuanxiao.dong@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      0e86cc9c
  24. 30 3月, 2017 3 次提交
  25. 29 3月, 2017 1 次提交
  26. 09 2月, 2017 1 次提交
  27. 07 2月, 2017 2 次提交
  28. 09 1月, 2017 1 次提交
  29. 10 11月, 2016 4 次提交