1. 07 1月, 2021 2 次提交
  2. 22 12月, 2020 1 次提交
  3. 16 12月, 2020 9 次提交
  4. 10 12月, 2020 2 次提交
  5. 09 12月, 2020 6 次提交
  6. 05 12月, 2020 1 次提交
    • M
      dm verity: Add support for signature verification with 2nd keyring · 4da8f8c8
      Mickaël Salaün 提交于
      Add a new configuration DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING
      to enable dm-verity signatures to be verified against the secondary
      trusted keyring.  Instead of relying on the builtin trusted keyring
      (with hard-coded certificates), the second trusted keyring can include
      certificate authorities from the builtin trusted keyring and child
      certificates loaded at run time.  Using the secondary trusted keyring
      enables to use dm-verity disks (e.g. loop devices) signed by keys which
      did not exist at kernel build time, leveraging the certificate chain of
      trust model.  In practice, this makes it possible to update certificates
      without kernel update and reboot, aligning with module and kernel
      (kexec) signature verification which already use the secondary trusted
      keyring.
      Signed-off-by: NMickaël Salaün <mic@linux.microsoft.com>
      Signed-off-by: NMike Snitzer <snitzer@redhat.com>
      4da8f8c8
  7. 04 12月, 2020 2 次提交
  8. 03 12月, 2020 1 次提交
  9. 02 12月, 2020 3 次提交
  10. 01 12月, 2020 2 次提交
  11. 25 11月, 2020 1 次提交
  12. 19 11月, 2020 3 次提交
    • M
      docs: bootconfig: Update file format on initrd image · fbc6e1c6
      Masami Hiramatsu 提交于
      To align the total file size, add padding null character when appending
      the bootconfig to initrd image.
      
      Link: https://lkml.kernel.org/r/160576522916.320071.4145530996151028855.stgit@devnote2Signed-off-by: NMasami Hiramatsu <mhiramat@kernel.org>
      Signed-off-by: NSteven Rostedt (VMware) <rostedt@goodmis.org>
      fbc6e1c6
    • N
      powerpc/64s: flush L1D after user accesses · 9a32a7e7
      Nicholas Piggin 提交于
      IBM Power9 processors can speculatively operate on data in the L1 cache
      before it has been completely validated, via a way-prediction mechanism. It
      is not possible for an attacker to determine the contents of impermissible
      memory using this method, since these systems implement a combination of
      hardware and software security measures to prevent scenarios where
      protected data could be leaked.
      
      However these measures don't address the scenario where an attacker induces
      the operating system to speculatively execute instructions using data that
      the attacker controls. This can be used for example to speculatively bypass
      "kernel user access prevention" techniques, as discovered by Anthony
      Steinhauser of Google's Safeside Project. This is not an attack by itself,
      but there is a possibility it could be used in conjunction with
      side-channels or other weaknesses in the privileged code to construct an
      attack.
      
      This issue can be mitigated by flushing the L1 cache between privilege
      boundaries of concern. This patch flushes the L1 cache after user accesses.
      
      This is part of the fix for CVE-2020-4788.
      Signed-off-by: NNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: NDaniel Axtens <dja@axtens.net>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      9a32a7e7
    • N
      powerpc/64s: flush L1D on kernel entry · f7964378
      Nicholas Piggin 提交于
      IBM Power9 processors can speculatively operate on data in the L1 cache
      before it has been completely validated, via a way-prediction mechanism. It
      is not possible for an attacker to determine the contents of impermissible
      memory using this method, since these systems implement a combination of
      hardware and software security measures to prevent scenarios where
      protected data could be leaked.
      
      However these measures don't address the scenario where an attacker induces
      the operating system to speculatively execute instructions using data that
      the attacker controls. This can be used for example to speculatively bypass
      "kernel user access prevention" techniques, as discovered by Anthony
      Steinhauser of Google's Safeside Project. This is not an attack by itself,
      but there is a possibility it could be used in conjunction with
      side-channels or other weaknesses in the privileged code to construct an
      attack.
      
      This issue can be mitigated by flushing the L1 cache between privilege
      boundaries of concern. This patch flushes the L1 cache on kernel entry.
      
      This is part of the fix for CVE-2020-4788.
      Signed-off-by: NNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: NDaniel Axtens <dja@axtens.net>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      f7964378
  13. 17 11月, 2020 1 次提交
  14. 10 11月, 2020 1 次提交
  15. 04 11月, 2020 2 次提交
  16. 03 11月, 2020 2 次提交
  17. 31 10月, 2020 1 次提交