1. 08 12月, 2006 6 次提交
    • R
      [IA64] Update processor_info features · 895309ff
      Russ Anderson 提交于
      Add the printing of additional processor features to proc_features.
      
      Based on Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software
      Developer's Manual" (January 2006) fields (pages 2:430-2:432).
      This patch gets the features back in sync with the spec.
      
      Sample output before:
      --------------------------------------------------------------
      cobra:~ # cat /proc/pal/cpu0/processor_info
      XIP,XPSR,XFS implemented                 : On NoCtrl
      XR1-XR3 implemented                      : On NoCtrl
      Disable dynamic predicate prediction     : NotImpl
      Disable processor physical number        : NotImpl
      Disable dynamic data cache prefetch      : NotImpl
      Disable dynamic inst cache prefetch      : NotImpl
      Disable dynamic branch prediction        : NotImpl
      Disable BINIT on processor time-out      : On Ctrl
      Disable dynamic power management (DPM)   : NotImpl
      Disable coherency                        : NotImpl
      Disable cache                            : NotImpl
      Enable CMCI promotion                    : Off Ctrl
      Enable MCA to BINIT promotion            : Off Ctrl
      Enable MCA promotion                     : NotImpl
      Enable BERR promotion                    : NotImpl
      cobra:~ #
      --------------------------------------------------------------
      
      Sample output after:
      --------------------------------------------------------------
      cobra:~ # cat /proc/pal/cpu0/processor_info
      Unimplemented instruction address fault  : NotImpl
      INIT, PMI, and LINT pins                 : NotImpl
      Simple unimplimented instr addresses     : On NoCtrl
      Variable P-state performance             : NotImpl
      Virtual machine features implemeted      : On NoCtrl
      XIP,XPSR,XFS implemented                 : On NoCtrl
      XR1-XR3 implemented                      : On NoCtrl
      Disable dynamic predicate prediction     : NotImpl
      Disable processor physical number        : NotImpl
      Disable dynamic data cache prefetch      : NotImpl
      Disable dynamic inst cache prefetch      : NotImpl
      Disable dynamic branch prediction        : NotImpl
      Disable P-states                         : Off Ctrl
      Enable MCA on Data Poisoning             : Off Ctrl
      Enable vmsw instruction                  : On Ctrl
      Enable extern environmental notification : NotImpl
      Disable BINIT on processor time-out      : On Ctrl
      Disable dynamic power management (DPM)   : NotImpl
      Disable coherency                        : NotImpl
      Disable cache                            : NotImpl
      Enable CMCI promotion                    : Off Ctrl
      Enable MCA to BINIT promotion            : Off Ctrl
      Enable MCA promotion                     : NotImpl
      Enable BERR promotion                    : NotImpl
      cobra:~ #
      --------------------------------------------------------------
      
      Signed-off-by: Russ Anderson (rja@sgi.com)
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      895309ff
    • R
      [IA64] Add se bit to Processor State Parameter structure · 6533bded
      Russ Anderson 提交于
      Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
      Manual" (January 2006) adds a se bit to the Processor State Parameter
      fields (pages 2:299).  This patch gets the structs back in sync
      with the spec.
      
      Signed-off-by: Russ Anderson (rja@sgi.com)
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      6533bded
    • R
      [IA64] Add dp bit to cache and bus check structs · 323cbb09
      Russ Anderson 提交于
      Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
      Manual" (January 2006) adds a dp bit to the cache_check and bus_check
      fields (pages 2:401-2:404).  This patch gets the structs back in sync
      with the spec.
      
      Signed-off-by: Russ Anderson (rja@sgi.com)
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      323cbb09
    • J
      [IA64] SN: Correctly update smp_affinty mask · c6957771
      John Keller 提交于
      On Altix systems, the /proc/irq/nn/smp_affinity mask is not being setup
      at device iniitalization, or updated after an interrupt redirection.
      This patch resolves those issues.
      Signed-off-by: NJohn Keller <jpk@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      c6957771
    • M
      [IA64] sparse cleanups · d61b49c1
      Matthew Wilcox 提交于
      0/NULL confusion and some missing UL on constants.
      Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      d61b49c1
    • Z
      [IA64] IA64 Kexec/kdump · a7956113
      Zou Nan hai 提交于
      Changes and updates.
      
      1. Remove fake rendz path and related code according to discuss with Khalid Aziz.
      2. fc.i offset fix in relocate_kernel.S.
      3. iospic shutdown code eoi and mask race fix from Fujitsu.
      4. Warm boot hook in machine_kexec to SN SAL code from Jack Steiner.
      5. Send slave to SAL slave loop patch from Jay Lan.
      6. Kdump on non-recoverable MCA event patch from Jay Lan
      7. Use CTL_UNNUMBERED in kdump_on_init sysctl.
      Signed-off-by: NZou Nan hai <nanhai.zou@intel.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      a7956113
  2. 07 12月, 2006 20 次提交
  3. 06 12月, 2006 14 次提交