This patch adds support for the GPIO functions of PPC40x and PPC44x
SOCs.
Signed-off-by: NSteve Falco <sfalco@harris.com>
Acked-by: NStefan Roese <sr@denx.de>
Acked-by: NSean MacLennan <smaclennan@pikatech.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

There is an old workaround in the sysdev/Makefile for dealing
with arch/ppc vs. arch/powerpc compiles.  This is no longer
needed as arch/ppc is dead.
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

Structured similar to the existing QE GPIO support.
Signed-off-by: NPeter Korsgaard <jacmet@sunsite.dk>
Acked-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

There are now two almost identical implementations of an MSI bitmap
allocator, one in mpic_msi.c and the other in fsl_msi.c.

Merge them together and put the result in msi_bitmap.c.  Some of the
MPIC bits will remain to provide a nicer interface for the MPIC users.

In the process we fix two buglets.  The first is that the allocation
routines, now msi_bitmap_alloc_hwirqs(), returned an unsigned result,
even though they use -1 to indicate allocation failure.  Although all
the callers were checking correctly, it is much better for the routine
to just return an int.  At least until someone wants > ~2 billion MSIs.

The second buglet is that the device tree reservation logic only
allowed power-of-two reservations.  AFAICT that didn't effect any
existing code but it's nicer if we can reserve arbitrary irqs from MSI
use.

We also add some selftests, which exposed the two buglets and now test
for them, as well as some basic sanity tests.  The tests are only built
when CONFIG_DEBUG_KERNEL=y.
Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Now that arch/ppc is gone and CONFIG_PPC_MERGE is always set, remove
the dead code associated with !CONFIG_PPC_MERGE from arch/powerpc
and include/asm-powerpc.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This is very trivial patch. We're transitioning to the cpm_muram_*
calls. That's it.

Less trivial changes:
- BD_SC_* defines were defined in the cpm.h and qe.h, so to avoid redefines
  we remove BD_SC from the qe.h and use cpm.h along with cpm_muram_*
  prototypes;
- qe_muram_dump was unused and thus removed;
- added some code to the cpm_common.c to support legacy QE bindings
  (data-only node name).
- For convenience, define qe_* calls to cpm_*. So drivers need not to be
  changed.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

GTM stands for General-purpose Timers Module and able to generate
timer{1,2,3,4} interrupts. These timers are used by the drivers that
need time precise interrupts (like for USB transactions scheduling for
the Freescale USB Host controller as found in some QE and CPM chips),
or these timers could be used as wakeup events from the CPU deep-sleep
mode.

Things unimplemented:
1. Cascaded (32 bit) timers (1-2, 3-4).
   This is straightforward to implement when needed, two timers should
   be marked as "requested" and configured as appropriate.
2. Super-cascaded (64 bit) timers (1-2-3-4).
   This is also straightforward to implement when needed, all timers
   should be marked as "requested" and configured as appropriate.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This MSI driver can be used on 83xx/85xx/86xx board.
In this driver, virtual interrupt host and chip were
setup. There are 256 MSI interrupts in this host, Every 32
MSI interrupts cascaded to one IPIC/MPIC interrupt.
The chip was treated as edge sensitive and some necessary
functions were setup for this chip.

Before using the MSI interrupt, PCI/PCIE device need to
ask for a MSI interrupt in the 256 MSI interrupts. A 256bit
bitmap show which MSI interrupt was used, reserve bit in
the bitmap can be used to force the device use some designate
MSI interrupt in the 256 MSI interrupts. Sometimes this is useful
for testing the all the MSI interrupts. The msi-available-ranges
property in the dts file was used for this purpose.
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This adds a function to put a 6xx/7xx/7xxx/83xx family CPU into sleep
mode, and return after an interrupt has occurred.  It expects to be
called with interrupts disabled, and returns with interrupts disabled.
Interrupts are enabled while the processor is asleep, but the interrupt
that wakes the processor is not handled; it is still pending when this
function returns.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Freescale UPM can be used to adjust localbus timings or to generate
orbitrary, pre-programmed "patterns" on the external Localbus signals.
This patch implements few routines so drivers could work with UPMs in
safe and generic manner.

So far there is just one user of these routines: Freescale UPM NAND
driver.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch adds support for the 256k L2 cache found on some IBM/AMCC
4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c)
which currently "only" adds the L2 cache init code. Other common 4xx
stuff can be added later here.

The L2 cache handling code is a copy of Eugene's code in arch/ppc
with small modifications.

Tested on AMCC Taishan 440GX.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Rename commproc.[ch] to cpm1.[ch] to be more consistent with cpm2. Also
rename cpm2_common.c to cpm2.c as suggested by Scott Wood. Adjust the
includes accordingly.
Signed-off-by: NJochen Friedrich <jochen@scram.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch extends the Ebony and Walnut platform code to instantiate
the existing ds1742 RTC class driver for the DS1743 RTC/NVRAM chip
found on both those boards.  The patch uses a helper function to scan
the device tree and instantiate the appropriate platform_device based
on it, so it should be easy to extend for other boards which have mmio
mapped RTC chips.

Along with this, the device tree binding for the ds1743 chips is
tweaked, based on the existing DS1385 OF binding found at:
	http://playground.sun.com/1275/proposals/Closed/Remanded/Accepted/346-it.txt
Although that document covers the NVRAM portion of the chip, whereas
here we're interested in the RTC portion, so it's not entirely clear
if that's a good model.

This implements only RTC class driver support - that is /dev/rtc0, not
/dev/rtc, and the low-level get/set time callbacks remain
unimplemented.  That means in order to get at the clock you will
either need a modified version of hwclock which will look at
/dev/rtc0, or you'll need to configure udev to symlink rtc0 to rtc.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Do just enough to move the RapidIO support code for 85xx over from arch/ppc
into arch/powerpc and make it still build.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

IPIC is not just for 83xx anymore so make it a separate config option.
Signed-off-by: NJohn Rigby <jrigby@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This adds base support code for the 4xx PCI-X bridge. It also provides
placeholders for the PCI and PCI-E version but they aren't supported
with this patch.

The bridges are configured based on device-tree properties.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Implement MSI support for PA Semi PWRficient platforms. MSI is done
through a special range of sources on the openpic controller, and they're
unfortunately breaking the usual concepts of how sources are programmed:

* The source is calculated as 512 + the value written into the MSI
  register
* The vector for this source is added to the source and reported
  through IACK

This means that for simplicity, it makes much more sense to just set the
vector to 0 for the source, since that's really the vector we expect to
see from IACK.

Also, the affinity/priority registers will affect 16 sources at a
time. To avoid most (simple) users from being limited by this, allocate
16 sources per device but use only one. This means that there's a total
of 32 sources.

If we get usage scenarions that need more sources, the allocator should
probably be revised to take an alignment argument and size, not just do
natural alignment.

Finally, since I'm already touching the MPIC names on pasemi, rename
the base one from the somewhat odd " PAS-OPIC  " to "PASEMI-OPIC".
Signed-off-by: NOlof Johansson <olof@lixom.net>
Acked-by: NMichael Ellerman <michael@ellerman.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This patch adds support for the core of the BestComm API
for the Freescale MPC5200(b). The BestComm engine is a
microcode-controlled / tasks-based DMA used by several
of the onchip devices.

Setting up the tasks / memory allocation and all common
low level functions are handled by this patch.
The specifics details of each tasks and their microcode
are split-out in separate patches.

This is not the official API, but a much cleaner one.
(hopefully)
Signed-off-by: NSylvain Munaut <tnt@246tNt.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

dcr.c is an arch/powerpc only thing.  Compiling ppc405 arch/ppc kernels
throws warnings without this change.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This code assumes that the ports have been previously set up, with
buffers in DPRAM.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Acked-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Adds support for the Xilinx opb-intc interrupt controller
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

With these functions implemented we cooperate better with the generic
timekeeping code.  This obsoletes the need for the timer sysdev as a bonus.
Signed-off-by: NTony Breeds <tony@bakeyournoodle.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Commit 69331af7, "Fixes and cleanups for earlyprintk aka boot console",
resulted in printk output prior to the initialization of the mpsc
console driver not being printed.  That commit causes the mpsc's
CON_PRINTBUFFER flag to be cleared since udbg should have printed
the previous output.

I guess we can no longer ignore udbg. :)

This patch provides udbg_putc() and udbg_getc() functions for the
Marvell mv64x60 chips. These functions are enabled if an mv64x60
port is to be used as the console as determined from the device tree.
Signed-off-by: NDale Farnsworth <dale@farnsworth.org>
Acked-by: NMark A. Greer <mgreer@mvista.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Move
arch/powerpc/platforms/86xx/pci.c -> arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pcie.h -> arch/powerpc/sysdev/fsl_pci.h
as the base to unify 83xx/85xx/86xx pci and pcie.

Add CONFIG_FSL_PCI to build fsl_pci.c for Freescale pci and pcie option.
The code still works for 86xx platforms.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The Axon bridge chip used on new Cell/B.E. based blade servers
comes with a DDR2 memory controller that can be used to
attach cheap memory modules, as opposed to the high-speed
XDR memory that is used by the CPU itself.

Since the memory controller does not participate in the
cache coherency protocol, we can not use the memory direcly
for Linux applications, but by providing a block device
it can be used for swap space, temporary file storage and
through the use of the direct_access block device operation
for mapping into user addresses, when it is mounted with
an appropriate file system.
Signed-off-by: NMaxim Shchetynin <maxim@de.ibm.com>
Signed-off-by: NArnd Bergmann <arnd.bergmann@de.ibm.com>

In order to use the RTC CMOS driver, each architecture must register a
platform device for the RTC.

This creates a function to register the platform device based on the RTC
device node and verifies that the RTC port against the hard-coded value
in asm/mc146818rtc.h.
Signed-off-by: NWade Farnsworth <wfarnsworth@mvista.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Remove errata for PCI-e support of Rev 1.0 of MPC8641 since its considered
obselete and is not production level silicon from Freescale.
Signed-off-by: NZhang Wei <wei.zhang@freescale.com>
Acked-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

There are times that we need to know which controller we are on to decide
how to exclude devices properly.  We now pass the pci_controller that we
are going to use down to the pci_exclude_device function. This will
greatly simplify being able to exclude the PHBs in multiple controller
setups.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

With both generic rtc and powerpc timer suspend / resume code now in the
(powerpc.git) tree, powerpc platforms using the generic timer and enabling
power management will have timer.o linked in the kernel, which they don't
need. Moreover, it will likely WARN_ON(!ppc_md.get_rtc_time), save
zero-time and return no error on suspend...

As a possible solution we can choose not to build timer.o when RTC_CLASS
is enabled.  However, I can imagine systems with 2 rtc's, one served by the
ppc-rtc, another one generic built as a module, in which case using the
ppc-rtc for suspend / resume will be impossible.  Not to say, that such a
configuration would be ugly...
Signed-off-by: NG. Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This patch adds PCI bridge support for the Marvell mv64x60 chip.
We also provide the ability to read/write the mv64x60 hotswap
register via sysfs if the hs_reg_valid property is set in the
device tree.
Signed-off-by: NDale Farnsworth <dale@farnsworth.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This patch creates platform_device entries for the Marvell mv64x60
MPSC (multi-protocol serial controller) ports, based on information
contained in the device tree.

This driver (like the other mv64x60 drivers) are unusual in that it
works on both the MIPS and PowerPC architectures.  Because of that,
the drivers do not support the normal PowerPC of_platform_bus_type.
They support platform_bus_type instead.
Signed-off-by: NDale Farnsworth <dale@farnsworth.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

There are 3 interrupt groups each with its own status/mask registers.
We use a separate struct irq_chip for each interrupt group and handle
interrupts in two stages or levels: level 1 selects the appropriate
struct irq_chip, and level 2 selects individual interrupts within
that irq_chip.
Signed-off-by: NDale Farnsworth <dale@farnsworth.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

powerpc_flash_init() implements a broken way of probing for flash
devices supported by the physmap_of driver.  It finds all nodes in the
device tree with device_type=="rom" and instantiates of_platform
devices for them.  This is fundamentally incompatible with the normal
and correct way of probing for of_platform_bus_probe().  Platforms
which relied on powerpc_flash_init()s behaviour (none are in-tree)
will have to update their platform probing code to correctly probe
busses containing flash devices.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

MPIC U3/U4 MSI backend. Based on code from Segher, heavily hacked by me.
This only deals with MSI on U3/U4 MPICs, aka. CPC 9x5.

If we find a U3/U4 then we enable this backend, ie. take over the ppc_md
MSI hooks. We might need more elaborate logic in future to decide which
backend is enabled.

We need our own irq_chip so that we can do MSI masking/unmasking on
the device itself. We also need to mask explicitly on shutdown to make
sure we don't get bitten by lazy-disable semantics.
Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

To support MSI on MPIC we need a way to reserve and allocate hardware irq
numbers, this patch implements an allocator for that purpose.

New firmware platforms must define a "msi-available-ranges" property on their
MPIC node for MSI to work. For U3/U4 we do a best-guess setup.
Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This patch adds a driver to arch/powerpc/sysdev for the UIC, the
on-chip interrupt controller from IBM/AMCC 4xx chips.  It uses the new
irq host mapping infrastructure.
Signed-off-by: NDavid Gibson <dwg@au1.ibm.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This move sets the stage for the use of generic PCI Express
code in 85xx and 86xx parts from FSL.  Subsequent patches
for 8548 and 8544 will be able to use this shared code.
Signed-off-by: NJon Loeliger <jdl@freescale.com>
Acked-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This removes the time suspend/restore code that was done through
a PMU notifier in arch/platforms/powermac/time.c.

Instead, introduce arch/powerpc/sysdev/timer.c which creates a sys
device and handles time of day suspend/resume through that.

This should probably be replaced by using the generic RTC framework
but for now it gets rid of the arcane powermac specific hack.
Signed-off-by: NJohannes Berg <johannes@sipsolutions.net>
Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This adds driver code for the PMI device found in future IBM products.
PMI stands for "Platform Management Interrupt" and is a way to
communicate with the BMC (Baseboard Management Controller).
It provides bidirectional communication with a low latency.
Signed-off-by: NChristian Krafft <krafft@de.ibm.com>
Acked-by: NArnd Bergmann <arnd.bergmann@de.ibm.com>
Acked-by: NHeiko J Schick <schickhj@de.ibm.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This covers common CPM access functions, CPM interrupt controller code,
micropatch and a few compatibility things to kee the same driver base
working with arch/ppc. This version is refined with all the comments
(mostly PIC-related) addressed.
Signed-off-by: NVitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>