1. 24 11月, 2021 1 次提交
  2. 23 11月, 2021 5 次提交
  3. 22 11月, 2021 1 次提交
  4. 19 11月, 2021 16 次提交
  5. 18 11月, 2021 2 次提交
    • H
      drm/i915/vlv_dsi: Double pixelclock on read-back for dual-link panels · 41211134
      Hans de Goede 提交于
      In intel_dsi_get_config() double the pclk returned by foo_dsi_get_pclk()
      for dual-link panels. This fixes the following WARN triggering:
      
       i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in pixel_rate (expected 235710, found 118056)
       i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in hw.pipe_mode.crtc_clock (expected 235710, found 118056)
       i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in hw.adjusted_mode.crtc_clock (expected 235710, found 118056)
       i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in port_clock (expected 235710, found 118056)
       ------------[ cut here ]------------
       pipe state doesn't match!
       WARNING: CPU: 3 PID: 136 at drivers/gpu/drm/i915/display/intel_display.c:9125 intel_display_finish_reset+0x1bd3/0x2050 [i915]
       ...
      
      This has been tested on a Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC) tablet,
      with a 1536x2048 dual-link DSI panel.
      
      Note this fix was taken from icl_dsi.c which does the same in
      its get_config().
      
      Cc: Tsuchiya Yuto <kitakar@gmail.com>
      Signed-off-by: NHans de Goede <hdegoede@redhat.com>
      Acked-by: NJani Nikula <jani.nikula@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20211024155020.126328-1-hdegoede@redhat.com
      41211134
    • I
      drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset · a59308a5
      Imre Deak 提交于
      After a non-blocking modeset on a TypeC port's CRTC - possibly blocked
      later in drm_atomic_helper_wait_for_dependencies() - a fastset on the
      same CRTC may copy the state of CRTC before this gets updated to reflect
      the up-to-date DP-alt vs. TBT-alt TypeC mode DPLL used for the CRTC. In
      this case after the first (non-blocking) commit completes enabling the
      DPLL required for the up-to-date TypeC mode the following fastset will
      update the CRTC state pointing to the wrong DPLL. A subsequent disabling
      modeset will try to disable the wrong PLL, triggering a state checker
      WARN (and leaving the DPLL which is actually used active for good).
      
      Fix the above race by copying the DPLL state for fastset CRTCs from the
      old CRTC state at the point where it's guaranteed to be up-to-date
      already. This could be handled in the encoder's update_prepare() hook as
      well, but that's a bigger change, which is better done as a follow-up.
      
      v2: Copy dpll_hw_state as well. (Ville)
      
      Testcase: igt/kms_busy/extended-modeset-hang-newfb-with-reset
      Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4308
      Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      Reviewed-by: NMika Kahola <mika.kahola@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20211115181121.156197-1-imre.deak@intel.com
      a59308a5
  6. 17 11月, 2021 7 次提交
  7. 16 11月, 2021 4 次提交
  8. 15 11月, 2021 3 次提交
  9. 12 11月, 2021 1 次提交