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  1. 22 10月, 2010 8 次提交
    • C
      [ARM] tegra: common: Update common clock init table · 8486bddc
      由 Colin Cross 提交于 
      Renames clocks in the clock init table to match the datasheet names
Signed-off-by: NColin Cross <ccross@android.com>
      8486bddc
    • C
      [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups · 71fc84cc
      由 Colin Cross 提交于 
      - Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
   PLLU is slightly different from the rest of the PLLs.  The
   lock enable bit is at bit 22 instead of 18 in the MISC
   register, and the post divider field is a single bit with
   reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops
Signed-off-by: NColin Cross <ccross@android.com>
      71fc84cc
    • C
      [ARM] tegra: Add support for reading fuses · 73625e3e
      由 Colin Cross 提交于 
      The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id.  The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: NColin Cross <ccross@android.com>
      73625e3e
    • C
      [ARM] tegra: gpio: Add suspend and wake support · 2e47b8b3
      由 Colin Cross 提交于 
      Includes checkpatch fixes and TEGRA_NR_GPIOS changes from
Mike Rapoport <mike@compulab.co.il>
Signed-off-by: NColin Cross <ccross@android.com>
      2e47b8b3
    • C
      [ARM] tegra: pinmux: add safe values, move tegra2, add suspend · c5f04b8d
      由 Colin Cross 提交于 
      - the reset values for some pin groups in the tegra pin mux can result in
functional errors due to conflicting with actively-configured pin groups
muxing from the same controller. this change adds a known safe, non-
conflicting mux for every pin group, which can be used on platforms
where the pin group is not routed to any peripheral

- also add each pin group's I/O voltage rail, to enable platform code to
map from the pin groups used by each interface to the regulators used
for dynamic voltage control

- add routines to individually configure the tristate, pin mux and pull-
ups for a pingroup_config array, so that it is possible to program
individual values at run-time without modifying other values.
this allows driver power-management code to reprogram individual
interfaces into lower power states during idle / suspend, or to
reprogram the pin mux to support multiple physical busses per
internal controller (e.g., sharing a single I2C or SPI controller
across multiple pin groups)

- move chip-specific data like pingroups and drive-pingroups
out of the common code and into chip-specific code

- fix debug output for group with no pullups

- add a TEGRA_MUX_SAFE function.  Setting a pingroup to TEGRA_MUX_SAFE
will automatically select a mux setting that is guaranteed not to
conflict with any of the hardware blocks.
Signed-off-by: NGary King <gking@nvidia.com>
      c5f04b8d
    • G
      [ARM] tegra: add suspend and mirror irqs to legacy controller · 460907bc
      由 Gary King 提交于 
      mirror IRQ enable and disable operations on the legacy PPI system
interrupt controller, since the legacy controller is responsible
for responding to wakeup interrupts when the CPU is in LP2 idle mode

save the irq controller state on suspend and restore on resume
Signed-off-by: NGary King <gking@nvidia.com>
      460907bc
    • C
      [ARM] tegra: Add legacy irq support · 8726e4f5
      由 Colin Cross 提交于 
      The "legacy irq controller" duplicates the functionality of the GIC,
but remains powered during the cpu suspend and idle modes that power
down the CPU and the GIC.
Signed-off-by: NColin Cross <ccross@android.com>
      8726e4f5
    • C
      [ARM] tegra: update iomap · c231d697
      由 Colin Cross 提交于 
      Add missing io address map entries from datasheet.
Add the IRAM area to the statically mapped io regions.
Correct the onewire, USB, and statmon addresses
Signed-off-by: NColin Cross <ccross@android.com>
      c231d697
  3. 21 10月, 2010 4 次提交
    • K
      security: remove unused parameter from security_task_setscheduler() · b0ae1981
      由 KOSAKI Motohiro 提交于 
      All security modules shouldn't change sched_param parameter of
security_task_setscheduler().  This is not only meaningless, but also
make a harmful result if caller pass a static variable.

This patch remove policy and sched_param parameter from
security_task_setscheduler() becuase none of security module is
using it.

Cc: James Morris <jmorris@namei.org>
Signed-off-by: NKOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Signed-off-by: NJames Morris <jmorris@namei.org>
      b0ae1981
    • F
      x86, mm: Enable ARCH_DMA_ADDR_T_64BIT with X86_64 || HIGHMEM64G · 66f2b061
      由 FUJITA Tomonori 提交于 
      Set CONFIG_ARCH_DMA_ADDR_T_64BIT when we set dma_addr_t to 64 bits in
<asm/types.h>; this allows Kconfig decisions based on this property.
Signed-off-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
LKML-Reference: <201010202255.o9KMtZXu009370@imap1.linux-foundation.org>
Acked-by: N"H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      66f2b061
    • S
      x86: Spread tlb flush vector between nodes · 93296720
      由 Shaohua Li 提交于 
      Currently flush tlb vector allocation is based on below equation:
	sender = smp_processor_id() % 8
This isn't optimal, CPUs from different node can have the same vector, this
causes a lot of lock contention. Instead, we can assign the same vectors to
CPUs from the same node, while different node has different vectors. This has
below advantages:
a. if there is lock contention, the lock contention is between CPUs from one
node. This should be much cheaper than the contention between nodes.
b. completely avoid lock contention between nodes. This especially benefits
kswapd, which is the biggest user of tlb flush, since kswapd sets its affinity
to specific node.

In my test, this could reduce > 20% CPU overhead in extreme case.The test
machine has 4 nodes and each node has 16 CPUs. I then bind each node's kswapd
to the first CPU of the node. I run a workload with 4 sequential mmap file
read thread. The files are empty sparse file. This workload will trigger a
lot of page reclaim and tlbflush. The kswapd bind is to easy trigger the
extreme tlb flush lock contention because otherwise kswapd keeps migrating
between CPUs of a node and I can't get stable result. Sure in real workload,
we can't always see so big tlb flush lock contention, but it's possible.

[ hpa: folded in fix from Eric Dumazet to use this_cpu_read() ]
Signed-off-by: NShaohua Li <shaohua.li@intel.com>
LKML-Reference: <1287544023.4571.8.camel@sli10-conroe.sh.intel.com>
Cc: Eric Dumazet <eric.dumazet@gmail.com>
Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      93296720
    • B
      x86, mm: Fix incorrect data type in vmalloc_sync_all() · f01f7c56
      由 Borislav Petkov 提交于 
      arch/x86/mm/fault.c: In function 'vmalloc_sync_all':
arch/x86/mm/fault.c:238: warning: assignment makes integer from pointer without a cast

introduced by 617d34d9.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <20101020103642.GA3135@kryptos.osrc.amd.com>
Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      f01f7c56
  5. 20 10月, 2010 28 次提交