This patch introduces PLL_I2S and PLL_SAI.
Vco clock of these PLLs can be modify by DT (only n multiplicator,
m divider is still fixed by the boot-loader).
Each PLL has 3 dividers. PLL should be off when we modify the rate.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NRob Herring <robh@kernel.org>
[sboyd@codeaurora.org: Mark stm32f4_pll_div_ops static]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Creation of dt include file for specific stm32f4 clocks.
These specific clocks are not derived from system clock (SYSCLOCK)
We should use index 1 to use these clocks in DT.
e.g. <&rcc 1 CLK_LSI>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

best_rate is reported as potentially uninitialized by gcc.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 155e8b3b ("clk: bcm: Support rate change propagation on bcm2835 clocks")
Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some driver is using this type of DT bindings for clock (more detail,
see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt).

	sound_soc {
		...
		cpu {
			clocks = <&xxx>;
			...
		};
		codec {
			clocks = <&xxx>;
			...
		};
	};

Current driver in this case uses of_clk_get() for each node, but there
is no devm_of_clk_get() today.
OTOH, the problem of having devm_of_clk_get() is that it encourages the
use of of_clk_get() when clk_get() is more desirable.

Thus, this patch adds new devm_get_clk_from_chile() which explicitly
reads as get a clock from a child node of this device.
By this function, we can also use this type of DT bindings

	sound_soc {
		clocks = <&xxx>, <&xxx>;
		clock-names = "cpu", "codec";
		clock-ranges;
		...
		cpu {
			...
		};
		codec {
			...
		};
	};
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[sboyd@codeurora.org: Rename subject to clk + add API]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Free memory mapping, if probe is not successful.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Free memory mapping, if of_pll_div_clk_init is not successful.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Free memory and memory mapping , if mmp2_clk_init is not successful.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
[sboyd@codeaurora.org: Put return at the right place]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Free memory and memory mapping , if pxa910_clk_init is not successful.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Free memory, if init is not successful.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

It is likely that instead of '1>64', 'q>64' was expected.

Moreover, according to datasheet,
   http://www.ti.com/lit/ds/symlink/cdce925.pdf
   SCAS847I - JULY 2007 - REVISED OCTOBER 2016
PLL settings limits are: 16 <= q <= 63
So change the upper limit check from 64 to 63.
Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The broadcom clk driver Kconfig file selects and depends on the
COMMON_CLK_IPROC config for different SoC specific drivers. Let's
simplify this by always selecting the COMMON_CLK_IPROC config,
turning it into a set of library code. We still want to retain
the SoC specific options, so we leave those in place. Since we're
here we also drop COMMON_CLK dependency because that's implicitly
handled by including this file in drivers/clk/Kconfig in the
right place and also make CLK_BCM_KONA default to y on the
architecture it exists for instead of plain default y.

Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <ray.jui@broadcom.com>
Cc: Jon Mason <jonmason@broadcom.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Acked-by: NScott Wood <oss@buserror.net>
Signed-off-by: NTang Yuantian <yuantian.tang@nxp.com>
[sboyd@codeaurora.org: Sorted list]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Prevent creating clk alias for non existing gmac_gmii_ref_clk_div clock and,
this way, eliminate excessive error message during boot:

 "ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div"

Fixes: c097338e ("ARM: dts: dra7: cpsw: fix clocks tree")
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some peripheral clocks, like the VEC (Video EnCoder) clock need to be set
to a precise rate (in our case 108MHz). With the current implementation,
where peripheral clocks are not allowed to forward rate change requests
to their parents, it is impossible to match this requirement unless the
bootloader has configured things correctly, or a specific rate has been
assigned through the DT (with the assigned-clk-rates property).

Add a new field to struct bcm2835_clock_data to specify which parent
clocks accept rate change propagation, and support set rate propagation
in bcm2835_clock_determine_rate().
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
to zero when disabling the clock.

Make sure we preserve this value by reading the previous a2w_reg value
first and ORing the result with A2W_PLL_CHANNEL_DISABLE.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 41691b88 ("clk: bcm2835: Add support for programming the audio domain clocks")
Cc: <stable@vger.kernel.org>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The OMAP36xx DPLL5, driving EHCI USB, can be subject to a long-term
frequency drift. The frequency drift magnitude depends on the VCO update
rate, which is inversely proportional to the PLL divider. The kernel
DPLL configuration code results in a high value for the divider, leading
to a long term drift high enough to cause USB transmission errors. In
the worst case the USB PHY's ULPI interface can stop responding,
breaking USB operation completely. This manifests itself on the
Beagleboard xM by the LAN9514 reporting 'Cannot enable port 2. Maybe the
cable is bad?' in the kernel log.

Errata sprz319 advisory 2.1 documents PLL values that minimize the
drift. Use them automatically when DPLL5 is used for USB operation,
which we detect based on the requested clock rate. The clock framework
will still compute the PLL parameters and resulting rate as usual, but
the PLL M and N values will then be overridden. This can result in the
effective clock rate being slightly different than the rate cached by
the clock framework, but won't cause any adverse effect to USB
operation.
Signed-off-by: NRichard Watts <rrw@kynesim.co.uk>
[Upported from v3.2 to v4.9]
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: NLadislav Michl <ladis@linux-mips.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Fix bug https://bugzilla.kernel.org/show_bug.cgi?id=188561. Function
wm831x_clkout_is_prepared() returns "true" when it fails to read
CLOCK_CONTROL_1. "true" means the device is already prepared. So
return "true" on the read failure seems improper.
Signed-off-by: NPan Bian <bianpan2016@163.com>
Acked-by: NCharles Keepax <ckeepax@opensource.wolfsonmicro.com>
Fixes: f05259a6 ("clk: wm831x: Add initial WM831x clock driver")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add more data to 64bit SoCs for the cpufreq support.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Core support code for CPU frequency changes, which will be used by
the generic cpufreq driver.

The register view is different from the generic clk-mux; it has
a separate status register, and an update bit to load the register
setting.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Merge tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP),
a fix making sure the cpuclk rate is actually valid, before trying to
set it and a copy-paste fix for the rk3399's testclk.

* tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add clock controller for rk1108
  dt-bindings: add documentation for rk1108 cru
  clk: rockchip: add dt-binding header for rk1108
  clk: rockchip: fix copy-paste error in rk3399 testclk
  clk: rockchip: validity should be checked prior to cpu clock rate change

The venus video ip's internal core blocks are under the
control of the firmware and their powerdomains needs to be
'ON' only when used by the firmware. So putting it into
hw controlled mode lets this to happen, otherwise the firmware
hangs checking for this.
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some GDSCs might support a HW control mode, where in the power
domain (gdsc) is brought in and out of low power state (while
unsued) without any SW assistance, saving power.
Such GDSCs can be configured in a HW control mode when powered on
until they are explicitly requested to be powered off by software.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NSricharan R <sricharan@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-fixes:
  clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XX
  clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock
  clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it

With commit f4e87150 ("clk: iproc: Make clocks visible options"),
COMMON_CLK_IPROC gained a dependency on ARCH_BCM_IPROC, yet CLK_BCM_63XX
also selects that option, this causes the following Kconfig warning:

warning: (CLK_BCM_63XX) selects COMMON_CLK_IPROC which has unmet direct
dependencies ((ARCH_BCM_IPROC || COMPILE_TEST) && COMMON_CLK)

Fix this by adding proper depends for COMMON_CLK_IPROC

Fixes: f4e87150 ("clk: iproc: Make clocks visible options")
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Reviewed-by: NRay Jui <ray.jui@broadcom.com>
[sboyd@codeaurora.org: Drop default part as it's redundant]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control
register is called "LDO{1,2}_EN", and according to the BSP source code
from Allwinner [1], the LDOs are enabled during the clock's enabling
process.

The clock failed to generate output if the two LDOs are not enabled.

Add the two bits to the clock's gate bits, so that the LDOs are enabled
when the PLL is enabled.

[1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429

Fixes: d05c748b ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

There is no fixed divider on pllh_aux.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NEric Anholt <eric@anholt.net>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Fix the clk_hw references to the actual clocks and add a xlate function
to return the hw pointers from the already existing static array.
Reported-by: NMichael Scott <michael.scott@linaro.org>
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Fix the clk_hw references to the actual clocks and add a xlate function
to return the hw pointers from the already existing static array.
Reported-by: NMichael Scott <michael.scott@linaro.org>
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084
expects a clk_set_rate() on the sdcc rcg clk to set
a floor value of supported clk rate closest to the requested
rate, by looking up the frequency table.
So move all the sdcc rcgs on all these platforms to use the
newly introduced clk_rcg2_floor_ops
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Signed-off-by: NJeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The default behaviour with clk_rcg2_ops is for the
clk_round_rate()/clk_set_rate() to return/set a ceil clock
rate closest to the requested rate by looking up the corresponding
frequency table.
However, we do have some instances (mainly sdcc on various platforms)
of clients expecting a clk_set_rate() to set a floor value instead.
Add a new clk_rcg2_floor_ops to handle this for such specific
rcg instances
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Pull Exynos5433 SoC updates from Sylwester Nawrocki:

 - addition of missing documentation and DT properties for the CMU_AUD
   block source clocks,
 - correction of CMU_FSYS parent clock definition,
 - marking as critical clocks which have to be enabled in order
   to access control registers of child CMUs.

* tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung:
  clk: exynos5433: Mark some clocks as critical
  clk: exynos5433: Add documentation for the audio block parent clocks
  clk: exynos5433: Fix parent clocks for FSYS block

The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.

Add the 2 LDO enable bits to the gate bits. This fixes issues with
the TCON not sending vblank interrupts when the tcon and dot clock are
indirectly clocked from the PLL-MIPI clock.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some parent clocks of the Exynos5433 CMUs must be always enabled to access
any register in the given CMU or devices connected to it. For the time
being, until a proper solution based on runtime PM is applied, mark those
clocks as critical (instead of ignore unused) to prevent disabling them.
Reported-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Merge tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull more clk driver updates from Geert Uytterhoeven:

  - CSI2 and VIN clocks for R-Car M3-W,
  - Clock drivers for new RZ/G1M and RZ/G1E SoCs,
  - Minor bug fix for R-Car H3.

* tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Add R8A7745 support
  clk: renesas: cpg-mssr: Add R8A7743 support
  clk: renesas: cpg-mssr: Add common R-Car Gen2 support
  clk: renesas: r8a7795: Fix HDMI parent clock
  clk: renesas: r8a7796: Add VIN clocks
  clk: renesas: r8a7796: Add CSI2 clocks

Merge tag 'clk-renesas-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geerty Uytterhoeven:

  - Add R-Car RST driver for obtaining mode pin state, and move the
    related functionality from platform code to DT,
  - Add r8a7743 and r8a7745 CPG Core Clock Definitions.

The commits here are intermingled with arm-soc material because
of the hard dependency we're breaking between mach code and
driver code. We're replacing that with a driver dependency
between the soc driver and the clk driver.

* tag 'clk-renesas-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (25 commits)
  clk: renesas: Add r8a7745 CPG Core Clock Definitions
  clk: renesas: Add r8a7743 CPG Core Clock Definitions
  clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init()
  clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init()
  clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init()
  ARM: shmobile: rcar-gen2: Stop passing mode pins state to clock driver
  ARM: shmobile: r8a7779: Stop passing mode pins state to clock driver
  ARM: shmobile: r8a7778: Stop passing mode pins state to clock driver
  clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()
  clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver
  clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driver
  clk: renesas: rcar-gen2: Obtain mode pin values using RST driver
  clk: renesas: r8a7779: Obtain mode pin values from R-Car RST driver
  clk: renesas: r8a7778: Obtain mode pin values using R-Car RST driver
  arm64: renesas: r8a7796 dtsi: Add device node for RST module
  arm64: renesas: r8a7795 dtsi: Add device node for RST module
  ARM: dts: r8a7794: Add device node for RST module
  ARM: dts: r8a7793: Add device node for RST module
  ARM: dts: r8a7792: Add device node for RST module
  ARM: dts: r8a7791: Add device node for RST module
  ...

Audio block requires access to two parent clocks: audio PLL and oscillator,
so add this information to device tree bindings documentation.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

The proper parent clock for FSYS block is "aclk_fsys_200"
according to the Exynos5433 reference manual.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Some checkpatch warnings about spaces were missed and we didn't
mark two structs as static. Clean it up.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Merge tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Pull Allwinner clock changes from Maxime Ripard:

The usual patches from us, but most notably the introduction of the A64
clocks unit.

* tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks
  clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks
  clk: sunxi-ng: Add A64 clocks
  clk: sunxi-ng: Implement minimum for multipliers
  clk: sunxi-ng: Add minimums for all the relevant structures and clocks
  clk: sunxi-ng: Finish to convert to structures for arguments
  clk: sunxi-ng: Remove the use of rational computations
  clk: sunxi-ng: Rename the internal structures
  clk: sunxi: mod0: improve function-level documentation