Power on one plane after disable all the planes, for
a hw bug work around to resolve stutter efficiency issue.
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SMU can future lower voltages in long idle case when all display is off.

If all display output is turned off via DPMS, send display_count = 0
after all output are turned off.

otherwise send display_count msg before turning on display to make sure
SMU exit S0i2 state.  before is not neccessary as we are out of S0i2
when driver execute code, but send message before anyways for correctness.
Signed-off-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

There are different code to disable front end, it is
difficult to debug and adding new process.
This refactor makes all disable front end call the same
functions.
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

dc_link is at a higher level than link_encoder, and we only want
higher-level components to be able to access lower-level ones,
not the other way around.
Signed-off-by: NAndrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This feature synchronizes multiple displays with various timings
to a display with the highest refresh rate
it is enabled if edid caps flag multi_display_sync is set to one

There are limitations on refresh rates allowed
that can be synchronized. That would
prevent from underflow and other potential
corruptions.

Multi display synchronization is using the
same functions as timing_sync in order to minimize
redunduncy and decision to disable synchronization is
based on trigger parametre set in DM

Feature is developed for DCN1 and DCE11
Signed-off-by: NMikita Lipski <mikita.lipski@amd.com>
Reviewed-by: NMikita Lipski <Mikita.Lipski@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

A recent commit moved the backlight control code along with the register
defines, but did not move the power control code. This along with
remnant fields in the dce110_link_enc_registers struct made it so that
the code still compiled, but any attempts to access the
LVTMA_PWRSEQ_STATE register led to reading from an address of 0. This
patch corrects that.

Also, rename blacklight_control to edp_backlight_control (Typo fix).
Signed-off-by: NAndrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Rename all the dc validate_context to dc_state and
dc current_context to current_state.
Signed-off-by: NJerry Zuo <Jerry.Zuo@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NHersen Wu <hersenxs.wu@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

-Flattening core_dc to dc
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NEric Yang <Eric.Yang2@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/struct dc_stream/struct dc_stream_state/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/struct dc_stream_state_update/struct dc_stream_update/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/struct dc_stream_state_status/struct dc_stream_status/g'

Plus some manual changes
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/struct dc_surface/struct dc_plane_state/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/struct dc_plane_state_update/struct dc_surface_update/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/struct dc_plane_state_status/struct dc_surface_status/g'

find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
-o -name "*.cpp" -o -name "*.hpp" | \
xargs sed -i 's/struct dc_plane_state_dcc_cap/struct dc_surface_dcc_cap/g'
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NLeo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NEric Yang <Eric.Yang2@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NZeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: NZeyu Fan <Zeyu.Fan@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NEric Yang <Eric.Yang2@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Reviewed-by: NWesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: NVitaly Prosyak <Vitaly.Prosyak@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This change fixes dcn10 front end reset sequence. Previously we
would reset front end during flip which led to issues
in certain MPO and 4k/5k scenarios. We would also never properly
power gate our front end.
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

HDMI frame pack and DP frame alternate in band
Signed-off-by: NVitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This fixes on boot crush on Vega, Polaris with Dal3.
Signed-off-by: NZeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAmy Zhang <Amy.Zhang@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Implement core support to allow for FreeSync Auto Sweep to work
Signed-off-by: NEric Cook <Eric.Cook@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- Refacotr PSR to follow correct module pattern
- fix eDP only working on sink index 0.
Signed-off-by: NSylvia Tsai <sylvia.tsai@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NJordan Lazare <Jordan.Lazare@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

always take update lock instead of using HW built in update
lock trigger with write to primary_addr_lo.

we will be a little more inefficient with the extra registers
write to lock, but this simplify code and make it always correct.

Will revisit locking optimization once update sequence mature
Signed-off-by: NTony Cheng <tony.cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NJordan Lazare <Jordan.Lazare@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAnthony Koo <anthony.koo@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

1. remove the sleep mechanism while set_blank true from
the timing generator.
Since Hw sequencer is the one that manages the flow
he will be responsible for wait for blanck in a critical places.
Signed-off-by: NLeon Elazar <leon.elazar@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The dc_gamma in dc_surface will be programmed to the input
LUT if provided.  If dc_gamma is not provided in dc_surface
regamma may be used to emulate gamma.

Some refactor and cleanup included as well.
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>