1. 13 7月, 2022 1 次提交
    • K
      Intel: 5G ISA: x86: Enumerate AVX512 FP16 CPUID feature flag · 82b4f867
      Kyung Min Park 提交于
      mainline inclusion
      from mainline-5.11
      commit e1b35da5
      category: feature
      feature: SPR New instructions
      bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I596EH
      CVE: N/A
      
      Intel-SIG: commit e1b35da5 x86: Enumerate AVX512 FP16 CPUID feature flag
      Backport for SPR core 5G ISA support.
      
      -------------------------------------
      
      Enumerate AVX512 Half-precision floating point (FP16) CPUID feature
      flag. Compared with using FP32, using FP16 cut the number of bits
      required for storage in half, reducing the exponent from 8 bits to 5,
      and the mantissa from 23 bits to 10. Using FP16 also enables developers
      to train and run inference on deep learning models fast when all
      precision or magnitude (FP32) is not needed.
      
      A processor supports AVX512 FP16 if CPUID.(EAX=7,ECX=0):EDX[bit 23]
      is present. The AVX512 FP16 requires AVX512BW feature be implemented
      since the instructions for manipulating 32bit masks are associated with
      AVX512BW.
      
      The only in-kernel usage of this is kvm passthrough. The CPU feature
      flag is shown as "avx512_fp16" in /proc/cpuinfo.
      
      Signed-off-by: Kyung Min Park kyung.min.park@intel.com
      Acked-by: Dave Hansen dave.hansen@intel.com
      Reviewed-by: Tony Luck tony.luck@intel.com
      Message-Id: 20201208033441.28207-2-kyung.min.park@intel.com
      Acked-by: Borislav Petkov bp@suse.de
      Signed-off-by: Paolo Bonzini pbonzini@redhat.com
      Signed-off-by: Luming Yu luming.yu@intel.com
      82b4f867
  2. 06 7月, 2022 39 次提交