- 22 8月, 2013 8 次提交
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由 Maxime Ripard 提交于
The Cubieboard2 is the successor of the first Cubieboard, and shares the same hardware, except that the Allwinner A10 found initially has been replaced by an Allwinner A20. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The A20-olinuxino Micro has a LED connected to the PH2 pin. Use the gpio-led driver to enable the control over this LED. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
Instead of relying on the bootloader to mux the UART pins properly, do it on our own and register the rightful pins for the A20-olinuxino in the DT using pinctrl. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The UARTs on the A20 can be muxed to several pins. Add a few options to the DTSI so that we can start using them in the boards' DT. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The PIO controller is responsible for the GPIO/muxing/external interrupts handling. Now that we have support for the A20 pin set in the pinctrl driver, we can start using it in the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The A31 has a different set of pins than the one found on the A10 and A13. Now that we have support for the A31 pin set in the pinctrl driver, we can enable it in the DTSI with its own compatible. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 20 8月, 2013 2 次提交
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由 Maxime Ripard 提交于
The Olimex A20-Olinuxino is an open-hardware board based on the Allwinner A20 SoC, with most of the pins exported on headers, a 10/100M ethernet port, SATA, SD and uSD slots, etc. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The Allwinner A20 SoC is based on 2 Cortex A7, an ARM Mali GPU, and is built to be pin-compatible with the older Allwinner A10. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 17 8月, 2013 2 次提交
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由 Maxime Ripard 提交于
This platform from WITS is the evaluation board for the Allwinner A31. It features a quad-Cortex A7, 2048MB of RAM, NAND, USB, MMC, several UART, HDMI, a 2048 x 1536 10" screen, powered by a PowerVR, etc. Of course, most of these peripherals aren't supported yet, but support for those will come eventually. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The Allwinner A31 SoC is a multimedia SoC powered by 4 Cortex-A7 and a PowerVR GPU. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 14 8月, 2013 1 次提交
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由 Emilio López 提交于
This adds a device tree usable on Mele A1000 (and A2000, as it apparently is the same device except for the case). This device features one UART port, Ethernet, an AXP209 PMU on i2c0 and two user configurable LEDs. Signed-off-by: NEmilio López <emilio@elopez.com.ar> [maxime: fixed the soc node address] Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 11 8月, 2013 6 次提交
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由 Maxime Ripard 提交于
There was a typo in the base address used for the soc node in the A13 device tree. Fix it with the proper base address. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The reg property of the simple-bus driver is completely useless. Remove it from the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
There was a typo in the base address used for the soc node in the A10s device tree. Fix it with the proper base address. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The reg property of the simple-bus driver is completely useless. Remove it from the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
There was a typo in the base address used for the soc node in the A10 device tree. Fix it with the proper base address. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The reg property of the simple-bus driver is completely useless. Remove it from the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 24 7月, 2013 1 次提交
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由 Emilio López 提交于
Quoting from Documentation/leds/leds-class.txt: LED Device Naming ================= Is currently of the form: "devicename:colour:function" Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 15 7月, 2013 4 次提交
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由 Emilio López 提交于
This OLIMEX board has a AT24C16BN-SH EEPROM holding the MAC address. This patch adds the corresponding device tree node to reflect this. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Emilio López 提交于
This board from OLIMEX is using the three I2C controllers present on A10S: * I2C-0 connects to the AXP152 PMU * I2C-1 holds an AT24C16BN-SH EEPROM with the MAC address for ethernet * I2C-2 is used for UEXT modules. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Emilio López 提交于
Allwinner A10S has 3 I2C controllers embedded on it. Add them to the corresponding dtsi. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Emilio López 提交于
The information has been extracted from the A10S-OLinuXino-Micro schematics, as we do not have a user manual for A10S yet. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 13 7月, 2013 3 次提交
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由 Al Viro 提交于
[suggested by Rasmus Villemoes] make O_DIRECTORY | O_RDWR part of O_TMPFILE; that will fail on old kernels in a lot more cases than what I came up with. And make sure O_CREAT doesn't get there... Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
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由 Olof Johansson 提交于
OMAP recently changed how the platforms are configured, so OMAP2/3/4 SoC support is no longer enabled by default. Add them back. Enable new ethernet driver for sunxi. The i.MX console options moved due to resorting, no functional change. Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Vincent Stehlé 提交于
- Add i.MX serial console support. This gives us the boot messages on UART on e.g. the i.MX6Q sabre sd platform. - Add the necessary config options, to allow booting with NFS root on an i.MX6 sabre sd. - Add Freescale LPUART serial console support. This gives us the boot messages on UART on e.g. the Vybrid VF610 Tower board. Signed-off-by: NVincent Stehlé <vincent.stehle@freescale.com> Cc: Russell King <linux@arm.linux.org.uk> [olof: squashed three commits down to one] Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 12 7月, 2013 3 次提交
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由 Dave Hansen 提交于
I completely botched understanding the calling conventions of do_div(). I assumed that do_div() returned the result instead of realizing that it modifies its argument and returns a remainder. The side-effect from this would be bogus numbers for the "msecs" value in the warning messages: INFO: NMI handler (perf_event_nmi_handler) took too long to run: 0.114 msecs Note, there was a second fix posted by Stephane Eranian for a separate patch which I also botched: http://lkml.kernel.org/r/20130704223010.GA30625@quadSigned-off-by: NDave Hansen <dave.hansen@linux.intel.com> Cc: Dave Hansen <dave@sr71.net> Link: http://lkml.kernel.org/r/20130708214404.B0B6EA66@viggo.jf.intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
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由 Russell King 提交于
The watchdog infrastructure in Dove is no different from that in Orion5x or Kirkwood, so let's enable it for Dove. The only things missing are a few register settings in Dove's bridge-regs.h. Rather than duplicating the same register bit masks for the RSTOUTn_MASK and BRIDGE_CAUSE registers, move the definitions into the watchdog driver itself. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk> Acked-by: NJason Cooper <jason@lakedaemon.net> Tested-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
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由 Viresh Kumar 提交于
Interrupt request doesn't use the right API: The TWD watchdog uses a per-cpu interrupt (usually interrupt #30), and the GIC configuration should flag it as such. With this setup, request_irq() should fail, and the right API is request_percpu_irq(), together with enable_percpu_irq()/disable_percpu_irq(). Nothing ensures the userspace ioctl() will end-up kicking the watchdog on the right CPU. There are no users of this driver since a long time and it makes more sense to get rid of it as nobody is looking to fix it. In case somebody wakes up after this has been removed and needs it, please revert this driver and pick these updates (These were never pushed to mainline): http://comments.gmane.org/gmane.linux.ports.arm.kernel/245998Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
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- 11 7月, 2013 5 次提交
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由 Michel Lespinasse 提交于
Since all architectures have been converted to use vm_unmapped_area(), there is no remaining use for the free_area_cache. Signed-off-by: NMichel Lespinasse <walken@google.com> Acked-by: NRik van Riel <riel@redhat.com> Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: David Howells <dhowells@redhat.com> Cc: Helge Deller <deller@gmx.de> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Matt Turner <mattst88@gmail.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Eliezer Tamir 提交于
Rename LL_SO to BUSY_POLL_SO Rename sysctl_net_ll_{read,poll} to sysctl_busy_{read,poll} Fix up users of these variables. Fix documentation for sysctl. a patch for the socket.7 man page will follow separately, because of limitations of my mail setup. Signed-off-by: NEliezer Tamir <eliezer.tamir@linux.intel.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Olivier DANET 提交于
Commit e4c6bfd2 ("mm: rearrange vm_area_struct for fewer cache misses") changed the layout of the vm_area_struct structure, it broke several SPARC32 assembly routines which used numerical constants for accessing the vm_mm field. This patch defines the VMA_VM_MM constant to replace the immediate values. Signed-off-by: NOlivier DANET <odanet@caramail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Andreas Larsson 提交于
Even if data snooping is enabled, without separate snoop tags snooping will not work when the MMU is enabled. Signed-off-by: NAndreas Larsson <andreas@gaisler.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Chen Gang 提交于
For the related next strcpy(), the destination length is less than 512, but the source maximize length may be 'OPROMMAXPARAM' (4096) which is more than 512. One work flow may: openprom_sunos_ioctl() -> if (cmd == OPROMSETOPT) getstrings() -> will alloc buffer with size 'OPROMMAXPARAM'. opromsetopt() -> devide the buffer into 'var' and 'value' of_set_property() -> pass prom_setprop() -> pass ldom_set_var() And do not mind the additional 4 alignment buffer increasing, since 'sizeof(pkt) - sizeof(pkt.header)' is 4 alignment at least. Signed-off-by: NChen Gang <gang.chen@asianux.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 7月, 2013 5 次提交
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由 Michal Simek 提交于
The reason is that other applications like strace think that every __NR_xx is syscall. Also __NR_syscalls is not used by user applications/libs. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Jason Liu 提交于
When the local timer freq changed, the twd_update_frequency function should be run all the CPUs include itself, otherwise, the twd freq will not get updated and the local timer will not run correcttly. smp_call_function will run functions on all other CPUs, but not include himself, this is not correct,use on_each_cpu instead to fix this issue. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: stable@vger.kernel.org Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NJason Liu <r64343@freescale.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Fabio Estevam 提交于
imx_v6_v7_defconfig handles both multi-core and single-core SoCs, and it has CONFIG_SMP=y selected by default. With such config we cannot select ARM_ERRATA_364296, as it depends on !SMP. Let ARM_ERRATA_364296 be undependent on CONFIG_SMP, so that we can select this erratum for the ARM1136 SoCs, even if CONFIG_SMP=y is enabled. Reviewed-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Helge Deller 提交于
When running the LTP testsuite one may hit this kernel BUG() with the write06 testcase: kernel BUG at mm/filemap.c:2023! CPU: 1 PID: 8614 Comm: writev01 Not tainted 3.10.0-rc7-64bit-c3000+ #6 IASQ: 0000000000000000 0000000000000000 IAOQ: 00000000401e6e84 00000000401e6e88 IIR: 03ffe01f ISR: 0000000010340000 IOR: 000001fbe0380820 CPU: 1 CR30: 00000000bef80000 CR31: ffffffffffffffff ORIG_R28: 00000000bdc192c0 IAOQ[0]: iov_iter_advance+0x3c/0xc0 IAOQ[1]: iov_iter_advance+0x40/0xc0 RP(r2): generic_file_buffered_write+0x204/0x3f0 Backtrace: [<00000000401e764c>] generic_file_buffered_write+0x204/0x3f0 [<00000000401eab24>] __generic_file_aio_write+0x244/0x448 [<00000000401eadc0>] generic_file_aio_write+0x98/0x150 [<000000004024f460>] do_sync_readv_writev+0xc0/0x130 [<000000004025037c>] compat_do_readv_writev+0x12c/0x340 [<00000000402505f8>] compat_writev+0x68/0xa0 [<0000000040251d88>] compat_SyS_writev+0x98/0xf8 Reason for this crash is a gcc miscompilation in the fault handlers of pa_memcpy() which return the fault address instead of the copied bytes. Since this seems to be a generic problem with gcc-4.7.x (and below), it's better to simplify the fault handlers in pa_memcpy to avoid this problem. Here is a simple reproducer for the problem: int main(int argc, char **argv) { int fd, nbytes; struct iovec wr_iovec[] = { { "TEST STRING ",32}, { (char*)0x40005000,32} }; // random memory. fd = open(DATA_FILE, O_RDWR | O_CREAT, 0666); nbytes = writev(fd, wr_iovec, 2); printf("return value = %d, errno %d (%s)\n", nbytes, errno, strerror(errno)); return 0; } In addition, John David Anglin wrote: There is no gcc PR as pa_memcpy is not legitimate C code. There is an implicit assumption that certain variables will contain correct values when an exception occurs and the code randomly jumps to one of the exception blocks. There is no guarantee of this. If a PR was filed, it would likely be marked as invalid. Signed-off-by: NHelge Deller <deller@gmx.de> Signed-off-by: NJohn David Anglin <dave.anglin@bell.net> Cc: <stable@vger.kernel.org> # 3.8+ Signed-off-by: NHelge Deller <deller@gmx.de>
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由 John David Anglin 提交于
I still see the occasional random segv on rp3440. Looking at one of these (a code 15), it appeared the problem must be with the cache handling of anonymous pages. Reviewing this, I noticed that the space register %sr1 might be being clobbered when we flush an anonymous page. Register %sr1 is used for TLB purges in a couple of places. These purges are needed on PA8800 and PA8900 processors to ensure cache consistency of flushed cache lines. The solution here is simply to move the %sr1 load into the TLB lock region needed to ensure that one purge executes at a time on SMP systems. This was already the case for one use. After a few days of operation, I haven't had a random segv on my rp3440. Signed-off-by: NJohn David Anglin <dave.anglin@bell.net> Cc: <stable@vger.kernel.org> # 3.10 Signed-off-by: NHelge Deller <deller@gmx.de>
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