1. 07 5月, 2008 1 次提交
  2. 06 5月, 2008 1 次提交
    • S
      [POWERPC] 4xx: Fix problem with new TLB storage attibute fields on 440x6 core · a96df496
      Stefan Roese 提交于
      The new 440x6 core used on AMCC 460EX/GT introduces new storage attibure
      fields to the TLB2 word. Those are:
      
      Bit  11   12   13   14   15
           WL1  IL1I IL1D IL2I IL2D
      
      With these bits the cache (L1 and L2) can be configured in a more flexible
      way, instruction- and data-cache independently now. The "old" I and W bits
      are still available and setting these old bits will automically set these
      new bits too (for backward compatibilty).
      
      The current code does not clear these fields resulting in disabling the cache
      by chance. This patch now makes sure that these new bits are cleared when
      the TLB2 word is written.
      Signed-off-by: NStefan Roese <sr@denx.de>
      Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      a96df496
  3. 05 5月, 2008 30 次提交
  4. 04 5月, 2008 8 次提交