Tegra194 allows max of 64K bytes and Tegra186 and prior allows
max of 4K bytes of transfer per packet.

one sec timeout is not enough for transfers more than 10K bytes
at STD bus rate.

This patch updates I2C transfer timeout based on the transfer size
and I2C bus rate to allow enough time during max transfer size at
lower bus speed.
Acked-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This patch adds DMA support for Tegra I2C.

Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for
transfer size of the max FIFO depth and DMA mode is used for
transfer size higher than max FIFO depth to save CPU overhead.

PIO mode needs full intervention of CPU to fill or empty FIFO's
and also need to service multiple data requests interrupt for the
same transaction. This adds delay between data bytes of the same
transfer when CPU is fully loaded and some slave devices has
internal timeout for no bus activity and stops transaction to
avoid bus hang. DMA mode is helpful in such cases.

DMA mode is also helpful for Large transfers during downloading or
uploading FW over I2C to some external devices.

Tegra210 and prior Tegra chips use APBDMA driver which is replaced
with GPCDMA on Tegra186 and Tegra194.
This patch uses has_apb_dma flag in hw_feature to differentiate
DMA driver change between Tegra chipset.

APBDMA driver is registered from module-init level and this patch
also has a change to register I2C driver at module-init level
rather than subsys-init to avoid deferring I2C probe till APBDMA
driver is registered.
Acked-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Tested-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Tegra194 supports maximum 64K bytes per packet including 12 bytes of
packet header irrespective of PIO or DMA mode transfer.

This patch updates Tegra194 max write length to account for packet
header size for transfers.

Cc: stable@vger.kernel.org # 4.20+
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Tegra186 and prior supports maximum 4K bytes per packet transfer
including 12 bytes of packet header.

This patch fixes max write length limit to account packet header
size for transfers.

Cc: stable@vger.kernel.org # 4.4+
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Bus clear feature of Tegra I2C controller helps to recover from
bus hang when I2C master loses the bus arbitration due to the
slave device holding SDA LOW continuously for some unknown reasons.

Per I2C specification, the device that held the bus LOW should
release it within 9 clock pulses.

During bus clear operation, Tegra I2C controller sends 9 clock
pulses and terminates the transaction with STOP condition.
Upon successful bus clear operation, bus goes to idle state and
driver retries the transaction.
Acked-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This patch sorts all the include headers alphabetically for the
I2C Tegra driver.
Acked-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The latest documentation made it clear that we need to initialize the
TCYC value independently of DMA. The old code used TCYC06 (wrongly) for
non-DMA transfers. The new code sets TCYC up independently from DMA.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

I think it is clear enough if we have the explanation once and make it
clear it is applicable for both SCL and SDA. Reword it a little with
the help of Simon's native language skills :)
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

We measured the clock on a Lager and an Ebisu board. The new formula
gives better results for both. So after Gen3, switch to this formula for
all Gen2 SoCs.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

We could finally measure the clock on an Ebisu board. The new formula
gives way better results, i.e. 100kHz instead of 106kHz and 400kHz
instead of 387kHz. Switch to these formulas for all Gen3 SoCs.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Makes it easier to add new ones.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This augments the CBUS GPIO I2C driver to use GPIO
descriptors for clock, sel and data. We drop the platform
data that was only used for carrying GPIO numbers and
use machine descriptor tables instead.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Update copyright years and remove a comment which grew incorrect and
useless over time.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

There is no value in chronological sorting. Make it easier to follow for
humans.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Completion_done() is useless when we don't use its return value,
so we remove it.
Signed-off-by: Nqii wang <qii.wang@mediatek.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Different speeds have been defined by macros,
so we use macros definitions.
Signed-off-by: Nqii wang <qii.wang@mediatek.com>
Reviewed-by: NNicolas Boichat <drinkcat@chromium.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Less risk for duplications when adding new ones.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

And use kernel style for the remaining comments in the header.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This adds device tree probing support for the IOP3xx
I2C master.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

If an I2C adapter doesn't match the provided device tree node, also try
matching the parent's device tree node. This allows finding an adapter
based on the device node of the parent device that was used to register
it.

This fixes a regression on Tegra124-based Chromebooks (Nyan) where the
eDP controller registers an I2C adapter that is used to read to EDID.
After commit 993a815d ("dt-bindings: panel: Add missing .txt
suffix") this stopped working because the I2C adapter could no longer
be found. The approach in this patch fixes the regression without
introducing the issues that the above commit solved.

Fixes: 17ab7806 ("drm: don't link DP aux i2c adapter to the hardware device node")
Signed-off-by: NThierry Reding <treding@nvidia.com>
Tested-by: NTristan Bastian <tristan-c.bastian@gmx.de>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

We currently get the following error with pixcir_ts driver during a
suspend resume cycle:

omap_i2c 4802a000.i2c: controller timed out
pixcir_ts 1-005c: pixcir_int_enable: can't read reg 0x34 : -110
pixcir_ts 1-005c: Failed to disable interrupt generation: -110
pixcir_ts 1-005c: Failed to stop
dpm_run_callback(): pixcir_i2c_ts_resume+0x0/0x98
[pixcir_i2c_ts] returns -110
PM: Device 1-005c failed to resume: error -110

And at least am437x based devices with pixcir_ts will fail to resume
to a touchscreen that is configured as the wakeup-source in device
tree for these devices.

This is because pixcir_ts tries to reconfigure it's registers for
noirq suspend which fails. This also leaves i2c-omap in enabled state
for suspend.

Let's fix the pixcir_ts issue and make sure i2c-omap is suspended by
adding SET_NOIRQ_SYSTEM_SLEEP_PM_OPS.

Let's also get rid of some ifdefs while at it and replace them with
__maybe_unused as SET_RUNTIME_PM_OPS and SET_NOIRQ_SYSTEM_SLEEP_PM_OPS
already deal with the various PM Kconfig options.
Reported-by: NKeerthy <j-keerthy@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Acked-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

This commit removes hard-coded bus timeout value setting so that
it can be set by i2c-core-base.
Signed-off-by: NJae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Reviewed-by: NBrendan Higgins <brendanhiggins@google.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Update copyright years and add Renesas to it. Add/update comments to
make driver easier to understand.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Remove the do_while loop which was just there to have an easy exit with
"break;" and replace it with if-else-blocks which should make the state
machine clearer.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

In preparation to remove the do-while-loop.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

All state machines deal with pd->pos values. This helper function is an
exception and makes it only more confusing.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

It is clear that we always send the address in TX_FIRST and data in TX.
No need to pass it from the caller.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

It makes the code much easier comprehensible to explicitly code that the
first byte will be client address and all the following bytes are the
actual data.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

pd->pos won't be smaller than -1, so we can simplify the logic.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

When doing s2idle/s2ram on Salvator-X(S):

    WARNING: CPU: 2 PID: 971 at drivers/i2c/i2c-core-base.c:1869 __i2c_transfer+0x608/0x910
[...]
    Call trace:
     __i2c_transfer+0x608/0x910
     i2c_smbus_xfer_emulated+0x158/0x5b0
     __i2c_smbus_xfer+0x17c/0x818
     i2c_smbus_xfer+0x64/0x98
     i2c_smbus_read_byte_data+0x40/0x70
     cs2000_bset.isra.1+0x2c/0x68
     __cs2000_set_rate.constprop.7+0x80/0x148
     cs2000_resume+0x18/0x20
     dpm_run_callback+0x74/0x330
     device_resume_early+0xd4/0x120
     dpm_resume_early+0x158/0x4f8
     suspend_devices_and_enter+0x36c/0xd98
[...]

On second resume, the sound driver fails with:

    cs2000-cp 2-004f: pll lock failed
    rcar_sound ec500000.sound: can't use clk 1

As the CS2000 clock driver needs to send I2C messages during suspend,
the I2C controller driver should be suspended later, and resumed
earlier.  Fix this by using the noirq sleep ops instead of the normal
sleep ops, which are called after the late sleep ops, as used by the
CS2000 clock driver.

Fixes: 18569fa8 ("i2c: rcar: add suspend/resume support")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Change the call to PTR_ERR to access the value just tested by IS_ERR.

Fixes: 5b3a23a3 ("i2c: imx: notify about real errors on dma i2c_imx_dma_request")
Signed-off-by: NYueHaibing <yuehaibing@huawei.com>
Reviewed-by: NOleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NEsben Haabendal <esben@haabendal.dk>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Improve the error handling in i2c_imx_dma_request() and let it return an error
indication that the caller then can handle accordingly.
Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

At least on i.MX5x, the DMA events for I2C and SDHC use the same channel
and there can only be a single user. So in this case there should be no
message emitted that looks like an error if the I2C device doesn't have
an assigned DMA channel. In contrast real problems that were only
emitted at debug level before should be described at a higher level
to be better visible and so understandable.
Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Tegra194 supports maximum 64K Bytes transfer per packet.
Tegra186 and prior supports maximum 4K Bytes transfer per packet.

This patch fixes this payload difference between Tegra194 and prior
Tegra chipsets using separate i2c_adapter_quirks.
Signed-off-by: NSowjanya Komatineni <skomatineni@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

If adapter->retries is set to a minus value from user space via ioctl,
it will make __i2c_transfer and __i2c_smbus_xfer skip the calling to
adapter->algo->master_xfer and adapter->algo->smbus_xfer that is
registered by the underlying bus drivers, and return value 0 to all the
callers. The bus driver will never be accessed anymore by all users,
besides, the users may still get successful return value without any
error or information log print out.

If adapter->timeout is set to minus value from user space via ioctl,
it will make the retrying loop in __i2c_transfer and __i2c_smbus_xfer
always break after the the first try, due to the time_after always
returns true.
Signed-off-by: NYi Zeng <yizeng@asrmicro.com>
[wsa: minor grammar updates to commit message]
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org

Because the adapter will be set up before every transaction anyhow, we
just need to mark it as suspended to the I2C core.
Signed-off-by: NHiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Rejecting transfers should be handled by the core. Also, this will
ensure proper locking which was forgotten in this open coded version.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Rejecting transfers should be handled by the core. Also, this will
ensure proper locking which was forgotten in this open coded version.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

Rejecting transfers should be handled by the core.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NBaolin Wang <baolin.wang@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>

The pointer to a device is usually named 'dev'. These 'pdev' here look
much like copy&paste errors. Fix them to avoid confusion.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: NBaolin Wang <baolin.wang@linaro.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>