1. 18 9月, 2018 7 次提交
  2. 17 9月, 2018 12 次提交
  3. 14 9月, 2018 17 次提交
  4. 13 9月, 2018 4 次提交
    • H
      net: dsa: Add Lantiq / Intel DSA driver for vrx200 · 14fceff4
      Hauke Mehrtens 提交于
      This adds the DSA driver for the GSWIP Switch found in the VRX200 SoC.
      This switch is integrated in the DSL SoC, this SoC uses a GSWIP version
      2.1, there are other SoCs using different versions of this IP block, but
      this driver was only tested with the version found in the VRX200.
      Currently only the basic features are implemented which will forward all
      packages to the CPU and let the CPU do the forwarding. The hardware also
      support Layer 2 offloading which is not yet implemented in this driver.
      
      The GPHY FW loaded is now done by this driver and not any more by the
      separate driver in drivers/soc/lantiq/gphy.c, I will remove this driver
      is a separate patch. to make use of the GPHY this switch driver is
      needed anyway. Other SoCs have more embedded GPHYs so this driver should
      support a variable number of GPHYs. After the firmware was loaded the
      GPHY can be probed on the MDIO bus and it behaves like an external GPHY,
      without the firmware it can not be probed on the MDIO bus.
      
      The clock names in the sysctrl.c file have to be changed because the
      clocks are now used by a different driver. This should be cleaned up and
      a real common clock driver should provide the clocks instead.
      Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      14fceff4
    • H
      net: lantiq: Add Lantiq / Intel VRX200 Ethernet driver · fe1a5642
      Hauke Mehrtens 提交于
      This drives the PMAC between the GSWIP Switch and the CPU in the VRX200
      SoC. This is currently only the very basic version of the Ethernet
      driver.
      
      When the DMA channel is activated we receive some packets which were
      send to the SoC while it was still in U-Boot, these packets have the
      wrong header. Resetting the IP cores did not work so we read out the
      extra packets at the beginning and discard them.
      
      This also adapts the clock code in sysctrl.c to use the default name of
      the device node so that the driver gets the correct clock. sysctrl.c
      should be replaced with a proper common clock driver later.
      Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fe1a5642
    • H
      MIPS: lantiq: Do not enable IRQs in dma open · cc973aec
      Hauke Mehrtens 提交于
      When a DMA channel is opened the IRQ should not get activated
      automatically, this allows it to pull data out manually without the help
      of interrupts. This is needed for a workaround in the vrx200 Ethernet
      driver.
      Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
      Acked-by: NPaul Burton <paul.burton@mips.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      cc973aec
    • H
      geneve: add ttl inherit support · 52d0d404
      Hangbin Liu 提交于
      Similar with commit 72f6d71e ("vxlan: add ttl inherit support"),
      currently ttl == 0 means "use whatever default value" on geneve instead
      of inherit inner ttl. To respect compatibility with old behavior, let's
      add a new IFLA_GENEVE_TTL_INHERIT for geneve ttl inherit support.
      Reported-by: NJianlin Shi <jishi@redhat.com>
      Suggested-by: NJiri Benc <jbenc@redhat.com>
      Signed-off-by: NHangbin Liu <liuhangbin@gmail.com>
      Reviewed-by: NJiri Benc <jbenc@redhat.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      52d0d404