1. 26 4月, 2019 15 次提交
  2. 26 2月, 2019 3 次提交
    • S
      coresight: etm4x: Add support to enable ETMv4.2 · 5666dfd1
      Sai Prakash Ranjan 提交于
      SDM845 has ETMv4.2 and can use the existing etm4x driver.
      But the current etm driver checks only for ETMv4.0 and
      errors out for other etm4x versions. This patch adds this
      missing support to enable SoC's with ETMv4x to use same
      driver by checking only the ETM architecture major version
      number.
      
      Without this change, we get below error during etm probe:
      
      / # dmesg | grep etm
      [    6.660093] coresight-etm4x: probe of 7040000.etm failed with error -22
      [    6.666902] coresight-etm4x: probe of 7140000.etm failed with error -22
      [    6.673708] coresight-etm4x: probe of 7240000.etm failed with error -22
      [    6.680511] coresight-etm4x: probe of 7340000.etm failed with error -22
      [    6.687313] coresight-etm4x: probe of 7440000.etm failed with error -22
      [    6.694113] coresight-etm4x: probe of 7540000.etm failed with error -22
      [    6.700914] coresight-etm4x: probe of 7640000.etm failed with error -22
      [    6.707717] coresight-etm4x: probe of 7740000.etm failed with error -22
      
      With this change, etm probe is successful:
      
      / # dmesg | grep etm
      [    6.659198] coresight-etm4x 7040000.etm: CPU0: ETM v4.2 initialized
      [    6.665848] coresight-etm4x 7140000.etm: CPU1: ETM v4.2 initialized
      [    6.672493] coresight-etm4x 7240000.etm: CPU2: ETM v4.2 initialized
      [    6.679129] coresight-etm4x 7340000.etm: CPU3: ETM v4.2 initialized
      [    6.685770] coresight-etm4x 7440000.etm: CPU4: ETM v4.2 initialized
      [    6.692403] coresight-etm4x 7540000.etm: CPU5: ETM v4.2 initialized
      [    6.699024] coresight-etm4x 7640000.etm: CPU6: ETM v4.2 initialized
      [    6.705646] coresight-etm4x 7740000.etm: CPU7: ETM v4.2 initialized
      Signed-off-by: NSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
      Reviewed-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      5666dfd1
    • M
      ARM: 8837/1: coresight: etmv4: Update ID register table to add UCI support · 28941701
      Mike Leach 提交于
      Adds macro to enable UCI entries to be added to AMBA ID tables.
      
      Updates the ID register tables to contain a UCI entry for the A35 ETM
      device to allow correct matching of driver in the amba bus code.
      Signed-off-by: NMike Leach <mike.leach@linaro.org>
      Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
      Reviewed-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
      Tested-by: NSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
      Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
      28941701
    • M
      ARM: 8838/1: drivers: amba: Updates to component identification for driver matching. · e85fa28e
      Mike Leach 提交于
      The CoreSight specification (ARM IHI 0029E), updates the ID register
      requirements for components on an AMBA bus, to cover both traditional
      ARM Primecell type devices, and newer CoreSight and other components.
      
      The Peripheral ID (PID) / Component ID (CID) pair is extended in certain
      cases to uniquely identify components. CoreSight components related to
      a single function can share Peripheral ID values, and must be further
      identified using a Unique Component Identifier (UCI). e.g. the ETM, CTI,
      PMU and Debug hardware of the A35 all share the same PID.
      
      Bits 15:12 of the CID are defined to be the device class.
      Class 0xF remains for PrimeCell and legacy components.
      Class 0x9 defines the component as CoreSight (CORESIGHT_CID above)
      Class 0x0, 0x1, 0xB, 0xE define components that do not have driver support
      at present.
      Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
      
      The specification futher defines which classes of device use the standard
      CID/PID pair, and when additional ID registers are required.
      
      This patch introduces the amba_cs_uci_id structure which will be used in
      all coresight drivers for indentification via the private data pointer in
      the amba_id structure.
      
      Existing drivers that currently use the amba_id->data pointer for private
      data are updated to use the amba_cs_uci_id->data pointer. Macros and
      inline functions are added to simplify this code.
      Signed-off-by: NMike Leach <mike.leach@linaro.org>
      Reviewed-by: NMathieu Poirier <mathieu.poirier@linaro.org>
      Reviewed-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
      Tested-by: NSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
      Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
      e85fa28e
  3. 23 2月, 2019 1 次提交
  4. 08 2月, 2019 6 次提交
  5. 06 2月, 2019 3 次提交
    • M
      coresight: Use event attributes for sink selection · 22644392
      Mathieu Poirier 提交于
      This patch uses the information conveyed by perf_event::attr::config2
      to select a sink to use for the session.  That way a sink can easily be
      selected to be used by more than one source, something that isn't currently
      possible with the sysfs implementation.
      Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
      Reviewed-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
      Acked-by: NPeter Zijlstra <peterz@infradead.org>
      Cc: Adrian Hunter <adrian.hunter@intel.com>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Alexei Starovoitov <ast@kernel.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Namhyung Kim <namhyung@kernel.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-s390@vger.kernel.org
      Link: http://lkml.kernel.org/r/20190131184714.20388-4-mathieu.poirier@linaro.orgSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      22644392
    • M
      coresight: perf: Add "sinks" group to PMU directory · bb8e370b
      Mathieu Poirier 提交于
      Add a "sinks" directory entry so that users can see all the sinks
      available in the system in a single place.  Individual sink are added
      as they are registered with the coresight bus.
      
      Committer tests:
      
      Test built on a ubuntu 18.04 container with a cross build environment to
      arm64, the new field is there, need to find a machine with this feature
      to do further testing in the future.
      
        root@d15263e5734a:/git/perf# grep CORESIGHT /tmp/build/v5.0-rc2+/.config
        CONFIG_CORESIGHT=y
        CONFIG_CORESIGHT_LINKS_AND_SINKS=y
        CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
        CONFIG_CORESIGHT_CATU=y
        CONFIG_CORESIGHT_SINK_TPIU=y
        CONFIG_CORESIGHT_SINK_ETBV10=y
        CONFIG_CORESIGHT_SOURCE_ETM4X=y
        CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
        CONFIG_CORESIGHT_STM=y
        CONFIG_CORESIGHT_CPU_DEBUG=m
        root@d15263e5734a:/git/perf#
        root@d15263e5734a:/git/perf# file /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/*.o
        .../coresight/coresight-catu.o:               ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-cpu-debug.mod.o:      ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-cpu-debug.o:          ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-dynamic-replicator.o: ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-etb10.o:              ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-etm-perf.o:           ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-etm4x-sysfs.o:        ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-etm4x.o:              ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-funnel.o:             ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-replicator.o:         ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-stm.o:                ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-tmc-etf.o:            ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-tmc-etr.o:            ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-tmc.o:                ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight-tpiu.o:               ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/coresight.o:                    ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        .../coresight/of_coresight.o:                 ELF 64-bit MSB relocatable, ARM aarch64, version 1 (SYSV), not stripped
        root@d15263e5734a:/git/perf#
      
        root@d15263e5734a:/git/perf# pahole -C coresight_device /tmp/build/v5.0-rc2+/drivers/hwtracing/coresight/coresight.o
        struct coresight_device {
                struct coresight_connection * conns;             /*     0     8 */
                int                        nr_inport;            /*     8     4 */
                int                        nr_outport;           /*    12     4 */
                enum coresight_dev_type    type;                 /*    16     4 */
                union coresight_dev_subtype subtype;             /*    20     8 */
      
                /* XXX 4 bytes hole, try to pack */
      
                const struct coresight_ops  * ops;               /*    32     8 */
                struct device              dev;                  /*    40  1408 */
      
                /* XXX last struct has 7 bytes of padding */
      
                /* --- cacheline 22 boundary (1408 bytes) was 40 bytes ago --- */
                atomic_t *                 refcnt;               /*  1448     8 */
                bool                       orphan;               /*  1456     1 */
                bool                       enable;               /*  1457     1 */
                bool                       activated;            /*  1458     1 */
      
                /* XXX 5 bytes hole, try to pack */
      
                struct dev_ext_attribute * ea;                   /*  1464     8 */
      
                /* size: 1472, cachelines: 23, members: 12 */
                /* sum members: 1463, holes: 2, sum holes: 9 */
                /* paddings: 1, sum paddings: 7 */
        };
        root@d15263e5734a:/git/perf#
      Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
      Reviewed-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
      Acked-by: NPeter Zijlstra <peterz@infradead.org>
      Cc: Adrian Hunter <adrian.hunter@intel.com>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Alexei Starovoitov <ast@kernel.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Namhyung Kim <namhyung@kernel.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-s390@vger.kernel.org
      Link: http://lkml.kernel.org/r/20190131184714.20388-3-mathieu.poirier@linaro.orgSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      bb8e370b
    • M
      perf/aux: Make perf_event accessible to setup_aux() · 84001866
      Mathieu Poirier 提交于
      When pmu::setup_aux() is called the coresight PMU needs to know which
      sink to use for the session by looking up the information in the
      event's attr::config2 field.
      
      As such simply replace the cpu information by the complete perf_event
      structure and change all affected customers.
      Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org>
      Reviewed-by: NSuzuki Poulouse <suzuki.poulose@arm.com>
      Acked-by: NPeter Zijlstra <peterz@infradead.org>
      Cc: Adrian Hunter <adrian.hunter@intel.com>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Alexei Starovoitov <ast@kernel.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Namhyung Kim <namhyung@kernel.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-s390@vger.kernel.org
      Link: http://lkml.kernel.org/r/20190131184714.20388-2-mathieu.poirier@linaro.orgSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      84001866
  6. 06 12月, 2018 6 次提交
  7. 26 9月, 2018 6 次提交