1. 13 10月, 2007 1 次提交
  2. 23 8月, 2007 1 次提交
  3. 25 7月, 2007 1 次提交
  4. 22 7月, 2007 1 次提交
  5. 03 5月, 2007 1 次提交
  6. 13 3月, 2007 1 次提交
    • E
      [PATCH] msi: Safer state caching. · 392ee1e6
      Eric W. Biederman 提交于
      There are two ways pci_save_state and pci_restore_state are used.  As
      helper functions during suspend/resume, and as helper functions around
      a hardware reset event.  When used as helper functions around a hardware
      reset event there is no reason to believe the calls will be paired, nor
      is there a good reason to believe that if we restore the msi state from
      before the reset that it will match the current msi state.  Since arch
      code may change the msi message without going through the driver, drivers
      currently do not have enough information to even know when to call
      pci_save_state to ensure they will have msi state in sync with the other
      kernel irq reception data structures.
      
      It turns out the solution is straight forward, cache the state in the
      existing msi data structures (not the magic pci saved things) and
      have the msi code update the cached state each time we write to the hardware.
      This means we never need to read the hardware to figure out what the hardware
      state should be.
      
      By modifying the caching in this manner we get to remove our save_state
      routines and only need to provide restore_state routines.
      
      The only fields that were at all tricky to regenerate were the msi and msi-x
      control registers and the way we regenerate them currently is a bit dependent
      upon assumptions on how we use the allow msi registers to be configured and used
      making the code a little bit brittle.  If we ever change what cases we allow
      or how we configure the msi bits we can address the fragility then.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      Acked-by: NAuke Kok <auke-jan.h.kok@intel.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      392ee1e6
  7. 05 3月, 2007 1 次提交
    • E
      [PATCH] msi: sanely support hardware level msi disabling · f5f2b131
      Eric W. Biederman 提交于
      In some cases when we are not using msi we need a way to ensure that the
      hardware does not have an msi capability enabled.  Currently the code has been
      calling disable_msi_mode to try and achieve that.  However disable_msi_mode
      has several other side effects and is only available when msi support is
      compiled in so it isn't really appropriate.
      
      Instead this patch implements pci_msi_off which disables all msi and msix
      capabilities unconditionally with no additional side effects.
      
      pci_disable_device was redundantly clearing the bus master enable flag and
      clearing the msi enable bit.  A device that is not allowed to perform bus
      mastering operations cannot generate intx or msi interrupt messages as those
      are essentially a special case of dma, and require bus mastering.  So the call
      in pci_disable_device to disable msi capabilities was redundant.
      
      quirk_pcie_pxh also called disable_msi_mode and is updated to use pci_msi_off.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Michael Ellerman <michael@ellerman.id.au>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Greg KH <greg@kroah.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      f5f2b131
  8. 08 2月, 2007 4 次提交
  9. 02 12月, 2006 1 次提交
    • I
      PCI: switch pci_{enable,disable}_device() to be nestable · bae94d02
      Inaky Perez-Gonzalez 提交于
      Changes the pci_{enable,disable}_device() functions to work in a
      nested basis, so that eg, three calls to enable_device() require three
      calls to disable_device().
      
      The reason for this is to simplify PCI drivers for
      multi-interface/capability devices. These are devices that cram more
      than one interface in a single function. A relevant example of that is
      the Wireless [USB] Host Controller Interface (similar to EHCI) [see
      http://www.intel.com/technology/comms/wusb/whci.htm]. 
      
      In these kind of devices, multiple interfaces are accessed through a
      single bar and IRQ line. For that, the drivers map only the smallest
      area of the bar to access their register banks and use shared IRQ
      handlers. 
      
      However, because the order at which those drivers load cannot be known
      ahead of time, the sequence in which the calls to pci_enable_device()
      and pci_disable_device() cannot be predicted. Thus:
      
      1. driverA     starts     pci_enable_device()
      2. driverB     starts     pci_enable_device()
      3. driverA     shutdown   pci_disable_device()
      4. driverB     shutdown   pci_disable_device()
      
      between steps 3 and 4, driver B would loose access to it's device,
      even if it didn't intend to.
      
      By using this modification, the device won't be disabled until all the
      callers to enable() have called disable().
      
      This is implemented by replacing 'struct pci_dev->is_enabled' from a
      bitfield to an atomic use count. Each caller to enable increments it,
      each caller to disable decrements it. When the count increments from 0
      to 1, __pci_enable_device() is called to actually enable the
      device. When it drops to zero, pci_disable_device() actually does the
      disabling.
      
      We keep the backend __pci_enable_device() for pci_default_resume() to
      use and also change the sysfs method implementation, so that userspace
      enabling/disabling the device doesn't disable it one time too much.
      Signed-off-by: NInaky Perez-Gonzalez <inaky@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      bae94d02
  10. 27 9月, 2006 1 次提交
  11. 13 7月, 2006 1 次提交
    • K
      [PATCH] PCI: PCIE power management quirk · ffadcc2f
      Kristen Carlson Accardi 提交于
      When changing power states from D0->DX and then from DX->D0, some
      Intel PCIE chipsets will cause a device reset to occur.  This will
      cause problems for any D State other than D3, since any state
      information that the driver will expect to be present coming from
      a D1 or D2 state will have been cleared.  This patch addes a
      flag to the pci_dev structure to indicate that devices should
      not use states D1 or D2, and will set that flag for the affected
      chipsets.  This patch also modifies pci_set_power_state() so that
      when a device driver tries to set the power state on
      a device that is downstream from an affected chipset, or on one
      of the affected devices it only allows state changes to or
      from D0 & D3.  In addition, this patch allows the delay time
      between D3->D0 to be changed via a quirk.  These chipsets also
      need additional time to change states beyond the normal 10ms.
      Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      ffadcc2f
  12. 28 6月, 2006 1 次提交
  13. 22 6月, 2006 1 次提交
  14. 15 4月, 2006 1 次提交
  15. 24 3月, 2006 1 次提交
  16. 10 1月, 2006 1 次提交
  17. 05 1月, 2006 1 次提交
  18. 29 10月, 2005 1 次提交
    • B
      [PATCH] PCI: Block config access during BIST · e04b0ea2
      Brian King 提交于
      Some PCI adapters (eg.  ipr scsi adapters) have an exposure today in that they
      issue BIST to the adapter to reset the card.  If, during the time it takes to
      complete BIST, userspace attempts to access PCI config space, the host bus
      bridge will master abort the access since the ipr adapter does not respond on
      the PCI bus for a brief period of time when running BIST.  On PPC64 hardware,
      this master abort results in the host PCI bridge isolating that PCI device
      from the rest of the system, making the device unusable until Linux is
      rebooted.  This patch is an attempt to close that exposure by introducing some
      blocking code in the PCI code.  When blocked, writes will be humored and reads
      will return the cached value.  Ben Herrenschmidt has also mentioned that he
      plans to use this in PPC power management.
      Signed-off-by: NBrian King <brking@us.ibm.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      
       drivers/pci/access.c    |   89 ++++++++++++++++++++++++++++++++++++++++++++++++
       drivers/pci/pci-sysfs.c |   20 +++++-----
       drivers/pci/pci.h       |    7 +++
       drivers/pci/proc.c      |   28 +++++++--------
       drivers/pci/syscall.c   |   14 +++----
       include/linux/pci.h     |    7 +++
       6 files changed, 134 insertions(+), 31 deletions(-)
      e04b0ea2
  19. 10 9月, 2005 1 次提交
  20. 17 8月, 2005 2 次提交
  21. 12 7月, 2005 2 次提交
  22. 18 5月, 2005 1 次提交
  23. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4