As docg3 is intolerant against reentrancy, especially
because of its weird register access (ie. a register read is
performed by a first register write), each access to the
docg3 IO space must be locked.

Lock the IO space with a mutex, shared by all chips on the
same cascade, as they all share the same IO space.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Group floors into a common cascade structure. This will provide a common
structure to store common data to all cascaded docg3 chips, like IO
addressing, locking protection.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch takes into account checkpatch, sparse and ECC
comments.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@linux.intel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

As each docg3 chip has 2 protection areas (DPS0 and DPS1),
and because theses areas can prevent user access to the chip
data, add for each floor the sysfs entries which insert the
protection key into the right DPS.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: NIvan Djelic <ivan.djelic@parrot.com>
Reviewed-by: NMike Dunn <mikedunn@newsguy.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Docg3 chips can work in 3 modes : normal MLC mode, fast
mode and reliable mode. Normally, as docg3 is a MLC chip, it
should be configured to work in normal mode.

In both normal mode, each page is distinct. This
means that writing to page 12 of blocks 14,15 writes only to
that page, and reading from page 12 of blocks 14,15 reads
only from that page.

In reliable and fast modes, pages are coupled by pairs, and
are clones one of each other. This means that the available
capacity of the chip is halved. Pages are coupled in each
block, and page of index 2*n contains the same data as page
2*n+1 of the same block.

In fast mode, the reads occur a bit faster, but are a bit
less reliable that in normal mode.

When reading from page 2*n, the chip reads bytes from both
page 2*n and page 2*n+1, makes a logical and for each byte,
and returns the result. As programming a page means
"clearing bits", even if a bit was not cleared on one page
because the flash is worn out, the other page has the bit
cleared, and the result of the "AND" gives a correct result.

When writing to page 2*n, the chip writes data to both page
2*n and page 2*n+1.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: NIvan Djelic <ivan.djelic@parrot.com>
Reviewed-by: NMike Dunn <mikedunn@newsguy.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add functions to powerdown and powerup from suspend, in
order to save power.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: NIvan Djelic <ivan.djelic@parrot.com>
Reviewed-by: NMike Dunn <mikedunn@newsguy.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Credit for discovering the BCH algorith parameters, and bit
reversing algorithm is to be give to Mike Dunn and Ivan
Djelic.

The BCH correction code relied upon the BCH library, where
all data and ECC is bit-reversed. The BCH library works
correctly when each input byte is bit-reversed, and
accordingly ECC output is also bit-reversed.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: NIvan Djelic <ivan.djelic@parrot.com>
Reviewed-by: NMike Dunn <mikedunn@newsguy.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add OOB buffer area to store the OOB data until the actual
page is written, so that it can be completed by hardware ECC
generator.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: NIvan Djelic <ivan.djelic@parrot.com>
Reviewed-by: NMike Dunn <mikedunn@newsguy.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add the required registers and commands to erase and write
flash pages / blocks.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: NIvan Djelic <ivan.djelic@parrot.com>
Reviewed-by: NMike Dunn <mikedunn@newsguy.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add support for multiple floors, ie. cascaded docg3
chips. There might be 4 docg3 chips cascaded, sharing the
same address space, and providing up to 4 times the storage
capacity of a unique chip.

Each floor will be seen as an independant mtd device.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: NIvan Djelic <ivan.djelic@parrot.com>
Reviewed-by: NMike Dunn <mikedunn@newsguy.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

BCH registers are contiguous, not on every byte. Fix the
register definitions.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Reviewed-by: NIvan Djelic <ivan.djelic@parrot.com>
Reviewed-by: NMike Dunn <mikedunn@newsguy.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add support for DiskOnChip G3 chips. The support is quite
limited yet :
 - no flash writes/erases are implemented
 - ECC fixes are not implemented
 - powerdown is not implemented
 - IPL handling is not yet done

On the brighter side, the chip reading does work.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>