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  1. 09 4月, 2013 6 次提交
  3. 03 4月, 2013 20 次提交
  5. 01 4月, 2013 5 次提交
    • R
      ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass · 469d633d
      由 Rajendra Nayak 提交于 
      omap3_noncore_dpll_set_rate() attempts an enable of bypass clk as well
as ref clk for every .set_rate attempt on a noncore DPLL, regardless of
whether the .set_rate results in the DPLL being locked or put in bypass.
Early at boot, while some of these DPLLs are programmed and locked
(using .set_rate for the DPLL), this causes an ordering issue.

For instance, on OMAP5, the USB DPLL derives its bypass clk from ABE DPLL.
If a .set_rate of USB DPLL which programmes the M,N and locks it is called
before the one for ABE, the enable of USB bypass clk (derived from ABE DPLL)
then attempts to lock the ABE DPLL and fails as the M,N values for ABE
are yet to be programmed.

To get rid of this ordering needs, enable bypass clk for a DPLL as part
of its .set_rate only when its being put in bypass, and only enable the
ref clk when its locked.
Reported-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      469d633d
    • P
      ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0 · bd70f6eb
      由 Paul Walmsley 提交于 
      _pwrdm_save_clkdm_state_and_activate() tried to test one of its
unsigned arguments to determine whether it was less than zero.  Fix by
moving the error test to the caller.
Reported-by: NChen Gang <gang.chen@asianux.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      bd70f6eb
    • R
      ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag · 4280943b
      由 Rajendra Nayak 提交于 
      _HWMOD_WAKEUP_ENABLED is currently unused across the hwmod
framework. Just get rid of it, so we have one less flag to
worry about.
Tested-by: NVaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      4280943b
    • V
      ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk · da91b89e
      由 Vaibhav Hiremath 提交于 
      WDT1 module can take one of the below clocks as input functional
clock -
     - On-Chip 32K RC Osc [default/reset]
     - 32K from PRCM

The On-Chip 32K RC Osc clock is not an accurate clock-source as per
the design/spec, so as a result, for example, timer which supposed
to get expired @60Sec, but will expire somewhere ~@40Sec, which is
not expected by any use-case.

The solution here is to switch the input clock-source to PRCM
generated 32K clock-source during boot-time itself.
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Benoit Cousson <benoit.cousson@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
      da91b89e
    • V
      ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry · 05cf03b6
      由 Vaibhav Hiremath 提交于 
      This patch adds sysc definitions to the wdt1 hwmod entry, which in-turn
makes sure that sysc idle bit-fields are configured to valid state on
enable/disable callbacks.

With the recent submitted patch from Santosh Shilimkar,
"ARM: OMAP2+: hwmod: Don't call _init_mpu_rt_base if no sysc"
(commit: 4a98c2d89), it is required to add sysconf
information to each valid hwmod entry, else device will not be
come out from idle state properly and leads to below kernel
crash  -

[2.190237] Unhandled fault: external abort on non-linefetch (0x1028) at
0xf9e35034
[2.198325] Internal error: : 1028 [#1] SMP ARM
[2.203101] Modules linked in:
[2.206334] CPU: 0    Not tainted  (3.9.0-rc3-00059-gd114294#1)
[2.212679] PC is at omap_wdt_disable.clone.5+0xc/0x60
[2.218090] LR is at omap_wdt_probe+0x184/0x1fc
Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Benoit Cousson <benoit.cousson@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
      05cf03b6
  7. 30 3月, 2013 1 次提交
  9. 28 3月, 2013 1 次提交
  11. 26 3月, 2013 2 次提交
  13. 25 3月, 2013 2 次提交
  15. 23 3月, 2013 1 次提交
  17. 22 3月, 2013 2 次提交