1. 09 3月, 2006 23 次提交
  2. 08 3月, 2006 15 次提交
  3. 07 3月, 2006 2 次提交
    • C
      [ARM] 3352/1: DSB required for the completion of a TLB maintenance operation · 6a0e2430
      Catalin Marinas 提交于
      Patch from Catalin Marinas
      
      Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that
      the completion of a TLB maintenance operation is only guaranteed by
      the execution of a DSB (Data Syncronization Barrier, formerly Data
      Write Barrier or Drain Write Buffer).
      
      Note that a DSB is only needed in the flush_tlb_kernel_* functions
      since the completion is guaranteed by a mode change (i.e. switching
      back to user mode) for the flush_tlb_user_* functions.
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      6a0e2430
    • M
      [TG3]: Add DMA address workaround · 72f2afb8
      Michael Chan 提交于
      Add DMA workaround for chips that do not support full 64-bit DMA
      addresses.
      
      5714, 5715, and 5780 chips only support DMA addresses less than 40
      bits. On 64-bit systems with IOMMU, set the dma_mask to 40-bit so
      that pci_map_xxx() calls will map the DMA address below 40 bits if
      necessary. On 64-bit systems without IOMMU, set the dma_mask to
      64-bit and check for DMA addresses exceeding the limit in
      tg3_start_xmit().
      
      5788 only supports 32-bit DMA so need to set the mask appropriately
      also.
      
      Thanks to Chris Elmquist at SGI for reporting and helping to debug
      the problem on 5714.
      
      Thanks to David Miller for explaining the HIGHMEM and DMA stuff.
      Signed-off-by: NMichael Chan <mchan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      72f2afb8