Adjusts the minimum memory frequency when the cpu frequency
changes.  The values are currently hardcoded to a reasonable
default.  If memory frequency scaling is not enabled this
patch will have no effect.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Add clock ops on the emc peripheral clock that call into the
emc driver to update the memory controller registers for the
new frequency.  Tegra has an interlock between the clock
controller and the memory controller that prevents the new
register values from taking effect until the clock frequency
update occurs.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

The frequency memory bus on Tegra can be adjusted without
disabling accesses to memory by updating the memory
configuration registers from a per-board table, and then
changing the clock frequency.  The clock controller and
memory controller have an interlock that prevents the
new memory registers from taking effect until the
clock frequency change.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Remove unnecessary uses of #ifdef CONFIG_DEBUG_FS
Convert bool assignments from 1 to true
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Some clocks may have multiple downstream users that need to request a
higher clock rate.  Shared bus clocks provide a unique shared_bus_user
clock to each user.  The frequency of the bus is set to the highest
enabled shared_bus_user clock, with a minimum value set by the
shared bus.  Drivers can use clk_enable and clk_disable to enable
or disable their requirement, and clk_set_rate to set the minimum rate.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

During cpu frequency changes, take an extra reference to pllx so
that it doesn't turn off and on while the cpu is temporarily on
pllp.  If the cpu is moved to pllp permanently, pllx will be
turned off.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Give each clock its own lock, and remove all lock traversals from
parent to child clocks to prevent AB-BA deadlocks.

This brings the locking in line with the common struct clk
patches and should make conversion simple.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Creates a union of a struct for each type of clock to reduce memory
usage and clarify which members are used by all clocks and which are
used by a single type.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Make the static clocks look more like the array of clocks
so they can all be initalized with the same helper function.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

The existing version did not extend well to core dvfs, drop it
for now until the new clk api with clk_prepare and clk_unprepare
is ready and non-atomic clocks are possible.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Assume that any clock that has no enable op is always on.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

The PLL lock bits are not reliable, use per-PLL timeouts instead.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Drop the unnecessary pr_debug calls to avoid having to maintain them.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

When updating the CPU PLL frequency, keeping the PLL enabled avoids
ramping the PLL all the way down and back up again.  Remove the BUG_ON
in tegra2_pll_clk_set_rate to allow the rate to change while the PLL
is enabled.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Add a new 'reset' clk op. This can be provided for any clock,
not just peripherals.
Signed-off-by: NDima Zavin <dima@android.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

This seems to be a regression in 2.6.37.

We cannot use writel() here since the resulting wmb() calls l2x0_cache_sync()
which uses a spinlock and L1 cache may be off at this point.

http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/041909.htmlSigned-off-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>

If a request already in the queue is passed to tegra_dma_enqueue_req,
tegra_dma_req.node->{next,prev} will end up pointing to itself instead
of at tegra_dma_channel.list, which is the way a the end-of-list
should be set up. When the DMA request completes and is list_del'd,
the list head will still point at it, yet the node's next/prev will
contain the list poison values. When the next DMA request completes,
a kernel panic will occur when those poison values are dereferenced.

This makes the DMA driver more robust in the face of buggy clients.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>

Add basic support for CompuLab TrimSlice platform
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NColin Cross <ccross@android.com>

Adding one single defconfig for the tegra family of boards, to over time
cover the superset of supported platform and drivers.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NColin Cross <ccross@android.com>

Sometimes, due to high interrupt latency in the continuous mode
of DMA transfer, the half buffer complete interrupt is handled
after DMA has transferred the full buffer.  When this is detected,
stop DMA immediately and restart with the next buffer if the next
buffer is ready.

originally fixed by Victor(Weiguo) Pan <wpan@nvidia.com>

In place of using the simple spin_lock()/spi_unlock() in the
interrupt thread, using the spin_lock_irqsave() and
spin_unlock_irqrestore(). The lock is shared between the normal
process context and interrupt context.

originally fixed by Laxman Dewangan (ldewangan@nvidia.com)

The use of shadow registers caused memory corruption at physical
address 0 because the enable bit was not shadowed, and assuming it
needed to be set would enable an unconfigured dma block.  Most of the
register accesses don't need to know the previous state of the
registers, and the few places that do need to modify only a few bits
in the registers are the same ones that were sometimes incorrectly
setting the enable bit.  This patch convert tegra_dma_update_hardware
to set the entire register, and the other users to read-modify-write,
and drops the shadow registers completely.

Also fixes missing locking in tegra_dma_allocate_channel
Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NColin Cross <ccross@android.com>

On Tegra, calling clk_set_rate on the CPU clock may call into the
regulator API.  If the regulator driver that controls the CPU
voltage rail has been suspended, this can lead to attempted
communication with a hardware block that has already been turned
off.

Adds a SUSPEND_PREPARE notification hook to drop the frequency to
the lowest possible during suspend.

Also adds 216MHz (off of PLLP) as the lowest CPU frequency, which
allows PLLX to be turned off.
Signed-off-by: NColin Cross <ccross@android.com>

Adds gart, hdmi, avp, host1x, and pwm controllers to mach/iomap.h
Signed-off-by: NGary King <gking@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NColin Cross <ccross@android.com>

Implement read_persistent_clock by reading the Tegra RTC
registers that stay running during suspend.

Save and restore the timer configuration register in
suspend.
Signed-off-by: NColin Cross <ccross@android.com>

Adds missing drive pingroups, saves all drive pingroups in
suspend, and restores the pinmux registers in the proper order.
Signed-off-by: NGary King <gking@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>

Save and restore pll and osc state during suspend
Add digital audio clocks
Update clk dev associations
Correct max clock frequencies
Add pll_p as additional cpu clock state
Add values to plld table
Fix register offset for sdmmc4 clock
Add blink timer to tegra2_clocks
Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NColin Cross <ccross@android.com>

Fixes typo in INT_CPU1_PMU_INTR (original fix from Will Deacon)
Adds board irqs
Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

We reserve lowmem for the things that need it, like the ACPI
wakeup code, way early to guarantee availability.  This happens
before we set up the proper pagetables, so set_memory_x() has no
effect.

Until we have a better solution, use an initcall to mark the
wakeup code executable.
Originally-by: NMatthieu Castet <castet.matthieu@free.fr>
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
Cc: Matthias Hopf <mhopf@suse.de>
Cc: rjw@sisk.pl
Cc: Suresh Siddha <suresh.b.siddha@intel.com>
LKML-Reference: <4D4F8019.2090104@zytor.com>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

Spinlocks on shared processor partitions use H_YIELD to notify the
hypervisor we are waiting on another virtual CPU. Unfortunately this means
the hcall tracepoints can recurse.

The patch below adds a percpu depth and checks it on both the entry and
exit hcall tracepoints.
Signed-off-by: NAnton Blanchard <anton@samba.org>
Acked-by: NSteven Rostedt <rostedt@goodmis.org>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
CC: stable@kernel.org

When converting to the new cpumask code I screwed up:

-       if (cpu_isset(cpu, numa_cpumask_lookup_table[node])) {
-               cpu_clear(cpu, numa_cpumask_lookup_table[node]);
+       if (cpumask_test_cpu(cpu, node_to_cpumask_map[node])) {
+               cpumask_set_cpu(cpu, node_to_cpumask_map[node]);

This was introduced in commit 25863de0 (powerpc/cpumask: Convert NUMA code
to new cpumask API)

Fix it.
Signed-off-by: NAnton Blanchard <anton@samba.org>
Cc: <stable@kernel.org>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

There is no need to start up the timer and monitor topology changes on a
dedicated processor partition, so disable it.
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

The rest of the NUMA code expects an OF associativity property with
the first cell containing the length. Without this fix all topology changes
cause us to misparse the property and put the cpu into node 0.
Signed-off-by: NAnton Blanchard <anton@samba.org>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>