HT/VHT MCS rateset should be filled only for configured chainmask
rather that max supported chainmask. Fix that by checking configured
chainmask while filling HT/VHT MCS rate map.
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Removing supported chainmask fields as it can be always derived
from num_rf_chains.
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

For the messages from host to target, shadow copy of CE descriptors
are maintained in source ring. Before writing actual CE descriptor,
first shadow copy is filled and then it is copied to CE address space.
To optimize in download path and to reduce d-cache pressure, removing
shadow copy of CE descriptors. This will also reduce driver memory
consumption by 33KB during on device probing.
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

The physical address necessary to unmap DMA ('bufferp') is stored
in ath10k_skb_cb as 'paddr'. ath10k doesn't rely on the meta/transfer_id
when handling send completion (htc ep id is stored in sk_buff control
buffer). So the unused output arguments {bufferp, nbytesp and transfer_idp}
are removed from CE send completion. This change is needed before removing
the shadow copy of copy engine (CE) descriptors in follow up patch.
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

CE diag window access is serialized (it has to be by design) so
there's no way to get a different send completion. so there's no
need for post completion validation.
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Currently to avoid uncached memory access while filling up copy engine
descriptors, shadow descriptors are used. This can be optimized further
by removing shadow descriptors. To achieve that first shadow ring
dependency in ce_send is removed by creating local copy of the
descriptor on stack and make a one-shot copy into the "uncached"
descriptor.
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

This patch adds support for getting firmware debug stats in 10.4 fw.
Signed-off-by: NManikanta Pubbisetty <c_mpubbi@qti.qualcomm.com>
Signed-off-by: NTamizh chelvam <c_traja@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Add WMI-TLV and FW API support in ath10k testmode.
Ath10k can get right wmi command format from UTF image
to communicate UTF firmware.
Signed-off-by: NAlan Liu <alanliu@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

European Union has made it mandatory that all devices working in 2.4 GHz
has to adhere to the ETSI specification (ETSI EN 300 328 V1.9.1)
beginnig this year. The standard basically speaks about interferences
in 2.4Ghz band.
For example, when 802.11 device detects interference, TX must be stopped
as long as interference is present.

Adaptive CCA is a feature, when enabled the device learns from the
environment and configures CCA levels adaptively. This will improve
detecting interferences and the device can stop trasmissions till the
interference is present eventually leading to good performances in
varying interference conditions.

The patch includes code for enabling adaptive CCA for 10.2.4 firmware on
QCA988X.
Signed-off-by: NMaharaja <c_mkenna@qti.qualcomm.com>
Signed-off-by: NManikanta Pubbisetty <c_mpubbi@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

arm64 has requirement that all the dma operations have actual device.
Otherwise, following warnning message shown and dma allocation fails:

WARNING: CPU: 0 PID: 954 at arch/arm64/mm/dma-mapping.c:106 __dma_alloc+0x24c/0x258()
Use an actual device structure for DMA allocation
Modules linked in: wcn36xx wcn36xx_platform
CPU: 0 PID: 954 Comm: ifconfig Not tainted 4.0.0+ #14
Hardware name: Qualcomm Technologies, Inc. MSM 8916 MTP (DT)
Call trace:
[<ffffffc000089904>] dump_backtrace+0x0/0x124
[<ffffffc000089a38>] show_stack+0x10/0x1c
[<ffffffc000627114>] dump_stack+0x80/0xc4
[<ffffffc0000b2e64>] warn_slowpath_common+0x98/0xd0
[<ffffffc0000b2ee8>] warn_slowpath_fmt+0x4c/0x58
[<ffffffc00009487c>] __dma_alloc+0x248/0x258
[<ffffffbffc009270>] wcn36xx_dxe_allocate_mem_pools+0xc4/0x108 [wcn36xx]
[<ffffffbffc0079c4>] wcn36xx_start+0x38/0x240 [wcn36xx]
[<ffffffc0005f161c>] ieee80211_do_open+0x1b0/0x9a4
[<ffffffc0005f1e68>] ieee80211_open+0x58/0x68
[<ffffffc00051693c>] __dev_open+0xb0/0x120
[<ffffffc000516c10>] __dev_change_flags+0x88/0x150
[<ffffffc000516cf4>] dev_change_flags+0x1c/0x5c
[<ffffffc000570950>] devinet_ioctl+0x644/0x6f0
Signed-off-by: NYin, Fengwei <fengwei.yin@linaro.org>
Acked-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NKalle Valo <kvalo@codeaurora.org>

wcn36xx implements a ring buffer for transmitted frames for each
(high and low priority) DMA channel.  The ring buffers are lockless:
new frames are inserted at the head of the queue, while finished
packets are reaped from the tail.

Unfortunately, the list manipulations are missing any kind of barriers
so are susceptible to various races: for example, a TX completion
handler might read an updated desc->ctrl before the head has actually
advanced, and then null out the ctl->skb pointer while it is still
being used in the TX path.

Simplify things here by adding a spin lock when traversing the ring.
This change increased stability for me without adding any noticeable
overhead on my platform (xperia z).
Signed-off-by: NBob Copeland <me@bobcopeland.com>
Signed-off-by: NKalle Valo <kvalo@codeaurora.org>

Some of the ath9k_phyerr enums were wrong from the
beginning (and even before). Most of the time the
codes were used for counters to be displayed over
debugfs, which made this a non-functional issue.

Some (e.g. ATH9K_PHYERR_FALSE_RADAR_EXT) are used
for radar detection and require the correct code
to work as intended.

This patch includes:
a) fixes
  ATH9K_PHYERR_FALSE_RADAR_EXT:    24 => 36
  ATH9K_PHYERR_CCK_LENGTH_ILLEGAL: 32 => 28
  ATH9K_PHYERR_CCK_POWER_DROP:     33 => 29
  ATH9K_PHYERR_HT_CRC_ERROR:       34 => 32
  ATH9K_PHYERR_HT_LENGTH_ILLEGAL:  35 => 33
  ATH9K_PHYERR_HT_RATE_ILLEGAL:    36 => 34

b) extensions
  ATH9K_PHYERR_CCK_BLOCKER = 24
  ATH9K_PHYERR_HT_ZLF      = 35
  ATH9K_PHYERR_GREEN_FIELD = 37

Aside from the correction and completion made in
the enum, the patch also extends the display of
the related counters in the debugfs.
Signed-off-by: NZefir Kurtisi <zefir.kurtisi@neratec.com>
Signed-off-by: NKalle Valo <kvalo@codeaurora.org>

The patch makes debug stats prints fw specific by adding a new member
in wmi_ops. That way it's easier to add fw_stats support to 10.4 firmware.
Signed-off-by: NManikanta Pubbisetty <c_mpubbi@qti.qualcomm.com>
Signed-off-by: NTamizh Chelvam <c_traja@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

This patch disables PCI PS for QCA988X and QCA99X0, Since PCI PS is
validated for QCA6174, let it be enabled only for QCA6174. It would be
better to execute PCI PS related functions only for the supported devices.

PCI time out issue is observed with QCA99X0 on x86 platform, We will
disable PCI PS for QCA988X and QCA99X0 until PCI PS is properly implemented.

Taking and releasing ps_lock is causing higher CPU consumption. Michal Kazior
suggested ps_lock overhead to be reworked so that ath10k_pci_wake/sleep
functions are called less often, i.e. move the powersave logic up (only during
irq handling, tx path, submitting fw commands) but that's a bigger change and
can be implemented later.
Signed-off-by: NAnilkumar Kolli <akolli@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Since polling for tx completion is handled whenever target to host
messages are received, removing the unnecessary polling mechanism for
send completion at HTC level.
Reviewed-by: NMichal Kazior <michal.kazior@tieto.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Since polling for received messages not supported, remove unused
dl_is_polled.
Reviewed-by: NMichal Kazior <michal.kazior@tieto.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Currently target to host (T2H) HTT messages are received at copy engine 1.
These messages are processed by HTC layer in both host and target.
To avoid HTC level processing overhead in both host and target,
the unused copy engine 5 is being used for receiving HTT T2H messages.
This will speedup the receive data processing as well as htt tx completion.
Hence host and target copy engine configuration tables are updated
to enable CE5 pipe. The in-direction HTT mapping is now pointing to CE5
for all HTT T2H.

Moreover HTT send completion messages are polled from HTC handler
as CE 4 is not interrupt-driven. For faster tx completion, CE4 polling
needs to be done whenever CE pipe which transports HTT Rx (target->host)
is processed. This avoids overhead of polling HTT messages from HTC
layer. Servicing CE 4 faster is helping to solve "failed to transmit
packet, dropping: -105".
Reviewed-by: NMichal Kazior <michal.kazior@tieto.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Some special copy engines delivers messages directly to HTT by
bypassing HTC layer. Hence exporting tx_completion and rx_handler
for delivering the data to HTT layer.
Reviewed-by: NMichal Kazior <michal.kazior@tieto.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Register receive callbacks for every copy engines (CE) separately
instead of having common receive handler. Some of the copy engines
receives different type of messages (i.e HTT/HTC/pktlog) from target.
Hence to service them accordingly, register per copy engine receive
callbacks.
Reviewed-by: NMichal Kazior <michal.kazior@tieto.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Register send completion callbacks for every copy engines (CE) separately
instead of having common completion handler. Since some of the copy
engines delivers different type of messages, per-CE callbacks help to
service them differently.
Reviewed-by: NMichal Kazior <michal.kazior@tieto.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Export HTC layer tx and rx handlers. This will be used by HIF layer
for per-CE data processing. Instead of callback mechanism, HIF will
call appropriate upper layers API directly.
Reviewed-by: NMichal Kazior <michal.kazior@tieto.com>
Signed-off-by: NRajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

A small bugfix for commit ede6a5e7 ("ath9k: Add QCA956x HW support").
I guess I would have skipped renaming (that initial QCA956x commit has
been there already for almost a year with the "5g" in the name) and move
the call outside AR_SREV_9462_20_OR_LATER() to make it reachable.
Signed-off-by: NMiaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: NKalle Valo <kvalo@codeaurora.org>

rename the variable as preparation for using the array with 2.4 GHz
band, etc.
Signed-off-by: NMiaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: NKalle Valo <kvalo@codeaurora.org>

The FreeBSD driver [0] uses the same 2G values as for the AR9280 chips.
Using the same values in ath9k results in much better throughput for me.

Before this patch I had a huge amount of packet loss (sometimes up to
40%) and the max transfer speed was somewhere around 5Mbit/s. With this
patch applied I have zero packet loss and ten times the throughput.
My device uses a AR9227 which is the PCI variant of the AR9287.

[0] http://bxr.su/FreeBSD/sys/dev/ath/ath_hal/ar9002/ar9287.hSigned-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKalle Valo <kvalo@codeaurora.org>

The logic in the error-handling path of ath10k_mac_register() is
divergent from the logic in ath10k_mac_unregister().  Update the
ath10k_mac_register() error handling logic to align with the
ath10k_mac_unregister() logic.
Signed-off-by: NJeff Johnson <jjohnson@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

First remove the 'cooling_device#n' syslink created
for ath10k and then unregsiter from the thermal subsystem(cooling)
Signed-off-by: NMohammed Shafi Shajakhan <mohammed@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

QCA99X0 uses radio specific board names based on chip id and
board id combinations. We get these IDs from the target using BMI after otp.bin
has been started.

This patch reorders the call to the function ath10k_core_fetch_board_file
so that we have OTP binary before requesting for boardid-chipid. We get this
OTP data after parsing firmware-N.bin.

[kvalo@qca.qualcomm.com: try BMI_PARAM_GET_EEPROM_BOARD_ID with
 all boards and detect if command is not supported]
Signed-off-by: NManikanta Pubbisetty <c_mpubbi@qti.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

QCA6174 needs different board files based on board type. To make it easier to
distribute multiple board files and automatically choose correct board file
create a simple TLV file format following the same principles as with FW IEs.
The file is named board-2.bin and contain multiple board files. Each board file
then can have multiple names.

ath10k searches for file board-N.bin (where N is the interface version number
for the board file, just like we for firmware files) in /lib/firmware/*, for
example for qca99x0 it will try to find it here:

/lib/firmware/ath10k/QCA99X0/hw2.0/board-2.bin

If ath10k doesn't find board-2.bin then it will fallback to the old board.bin file.

This patch adds a simple name scheme using pci device id which for now will be
used by qca6174:

bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x

This removes the old method of having subsystem ids in ar->spec_board_id and
using that in the board file name.
Signed-off-by: NManikanta Pubbisetty <c_mpubbi@qti.qualcomm.com>
[kvalo@qca.qualcomm.com: simplified the file format, rewrote commit log, other smaller changes]
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Add the option to configure multiple 'scan plans' for scheduled scan.
Each 'scan plan' defines the number of scan cycles and the interval
between scans. The scan plans are executed in the order they were
configured. The last scan plan will always run infinitely and thus
defines only the interval between scans.
The maximum number of scan plans supported by the device and the
maximum number of iterations in a single scan plan are advertised
to userspace so it can configure the scan plans appropriately.

When scheduled scan results are received there is no way to know which
scan plan is being currently executed, so there is no way to know when
the next scan iteration will start. This is not a problem, however.
The scan start timestamp is only used for flushing old scan results,
and there is no difference between flushing all results received until
the end of the previous iteration or the start of the current one,
since no results will be received in between.
Signed-off-by: NAvraham Stern <avraham.stern@intel.com>
Signed-off-by: NLuca Coelho <luciano.coelho@intel.com>
Signed-off-by: NJohannes Berg <johannes.berg@intel.com>

WARN_ON() already contain an unlikely compiler flag. Drop it.
Signed-off-by: NGeliang Tang <geliangtang@163.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

The DFS pattern detector ought to reset the
detector lines when a pulse is added with
lower time stamp than the previous (which
indicates a TSF restart).

This did not work so far and is fixed with
this patch.

The modification does not change detection
performance within the driver, since it
only ensures early reset (which is later
performed by the PRI detectors anyway).
It is relevant for synthetic tests and
statistical evaluations, where millions
of pulse patterns are processed and an
early reset helps reducing load.
Signed-off-by: NZefir Kurtisi <zefir.kurtisi@neratec.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

The check for send_pkt being NULL is redundant before the call
to htc_reclaim_txctrl_buf, therefore it should be removed. This was
detected by static analysis by cppcheck.
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

During reset flow, ignore firmware errors detected prior
to the actual hardware reset as the recovery flow would
make additional unnecessary reset.
Signed-off-by: NHamad Kadmany <qca_hkadmany@qca.qualcomm.com>
Signed-off-by: NVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

When firmware crashes, just before firmware recovery,
dump the firmware memory to a devcoredump device.
The resulting dump can be read from user space to be used
in offline crash analysis.
Signed-off-by: NLior David <liord@codeaurora.org>
Signed-off-by: NVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Situations observed when IP stack schedules lots of
frames for Tx while no connection (connection lost,
for example). In this case, dmesg bloated with error
message "FW not connected", printed for every frame.

Ratelimit this error message to avoid dmesg pollution.
Signed-off-by: NVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

For the sniffer (monitor) mode, capture either control only or both
control and data PHY.

It used to be control only or data only PHY due to firmware
issues with configuration for PHY auto-detection; but now
it is resolved.
Signed-off-by: NVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

BAR frames delivered to the host via Rx path; whole BAR frame
get delivered. Advance sequence in the reorder buffer and release
old frames, as per IEEE802.11 spec.

Firmware will reply to BAR, driver responsibility is only reorder
buffer management.
Signed-off-by: NVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Hostapd request disconnect for broadcast bssid when it
wants to disconnect all stations from the AP.

Detect this and really disconnect all connected stations.
Signed-off-by: NVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

When allocating pmc descriptor, the structure is
initially created on stack and later copied to
the physical ring (device) memory. The descriptor
structure must be initialized to zero to avoid
garbage configuration, which may result in pmc
mechanism malfunctioning.
Signed-off-by: NVladimir Shulman <QCA_shulmanv@QCA.qualcomm.com>
Signed-off-by: NVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>

Print firmware and ucode assert codes when firmware crashed.
Signed-off-by: NLior David <liord@qti.qualcomm.com>
Signed-off-by: NVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: NKalle Valo <kvalo@qca.qualcomm.com>