1. 01 1月, 2019 1 次提交
  2. 07 12月, 2018 1 次提交
  3. 06 12月, 2018 2 次提交
  4. 05 12月, 2018 4 次提交
    • F
      ARM: dts: imx7d-pico: Describe the Wifi clock · c3b9ab5d
      Fabio Estevam 提交于
      The Wifi chip should be clocked by a 32kHz clock coming from i.MX7D
      CLKO2 output pin, so describe the pinmux and clock hierarchy in the
      device tree to allow the Wifi chip to be properly clocked.
      
      Managed to successfully test Wifi with such change. Used the standard
      nvram.txt file provided by TechNexion, which selects an external 32kHz
      clock for the Wifi chip by default.
      
      Fixes: 99a52450 ("ARM: dts: imx7d-pico: Add Wifi support")
      Suggested-by: NArend van Spriel <arend.vanspriel@broadcom.com>
      Tested-by: NOtavio Salvador <otavio@ossystems.com.br>
      Signed-off-by: NFabio Estevam <festevam@gmail.com>
      Signed-off-by: NShawn Guo <shawnguo@kernel.org>
      c3b9ab5d
    • N
      ARM: 8816/1: dma-mapping: fix potential uninitialized return · c2a3831d
      Nathan Jones 提交于
      While trying to use the dma_mmap_*() interface, it was noticed that this
      interface returns strange values when passed an incorrect length.
      
      If neither of the if() statements fire then the return value is
      uninitialized. In the worst case it returns 0 which means the caller
      will think the function succeeded.
      
      Fixes: 1655cf88 ("ARM: dma-mapping: Remove traces of NOMMU code")
      Signed-off-by: NNathan Jones <nathanj439@gmail.com>
      Reviewed-by: NRobin Murphy <robin.murphy@arm.com>
      Acked-by: NVladimir Murzin <vladimir.murzin@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
      c2a3831d
    • V
      ARM: 8815/1: V7M: align v7m_dma_inv_range() with v7 counterpart · 3d0358d0
      Vladimir Murzin 提交于
      Chris has discovered and reported that v7_dma_inv_range() may corrupt
      memory if address range is not aligned to cache line size.
      
      Since the whole cache-v7m.S was lifted form cache-v7.S the same
      observation applies to v7m_dma_inv_range(). So the fix just mirrors
      what has been done for v7 with a little specific of M-class.
      
      Cc: Chris Cole <chris@sageembedded.com>
      Signed-off-by: NVladimir Murzin <vladimir.murzin@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
      3d0358d0
    • C
      ARM: 8814/1: mm: improve/fix ARM v7_dma_inv_range() unaligned address handling · a1208f6a
      Chris Cole 提交于
      This patch addresses possible memory corruption when
      v7_dma_inv_range(start_address, end_address) address parameters are not
      aligned to whole cache lines. This function issues "invalidate" cache
      management operations to all cache lines from start_address (inclusive)
      to end_address (exclusive). When start_address and/or end_address are
      not aligned, the start and/or end cache lines are first issued "clean &
      invalidate" operation. The assumption is this is done to ensure that any
      dirty data addresses outside the address range (but part of the first or
      last cache lines) are cleaned/flushed so that data is not lost, which
      could happen if just an invalidate is issued.
      
      The problem is that these first/last partial cache lines are issued
      "clean & invalidate" and then "invalidate". This second "invalidate" is
      not required and worse can cause "lost" writes to addresses outside the
      address range but part of the cache line. If another component writes to
      its part of the cache line between the "clean & invalidate" and
      "invalidate" operations, the write can get lost. This fix is to remove
      the extra "invalidate" operation when unaligned addressed are used.
      
      A kernel module is available that has a stress test to reproduce the
      issue and a unit test of the updated v7_dma_inv_range(). It can be
      downloaded from
      http://ftp.sageembedded.com/outgoing/linux/cache-test-20181107.tgz.
      
      v7_dma_inv_range() is call by dmac_[un]map_area(addr, len, direction)
      when the direction is DMA_FROM_DEVICE. One can (I believe) successfully
      argue that DMA from a device to main memory should use buffers aligned
      to cache line size, because the "clean & invalidate" might overwrite
      data that the device just wrote using DMA. But if a driver does use
      unaligned buffers, at least this fix will prevent memory corruption
      outside the buffer.
      Signed-off-by: NChris Cole <chris@sageembedded.com>
      Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
      a1208f6a
  5. 04 12月, 2018 3 次提交
  6. 28 11月, 2018 1 次提交
    • S
      ARM: function_graph: Simplify with function_graph_enter() · f1f5b14a
      Steven Rostedt (VMware) 提交于
      The function_graph_enter() function does the work of calling the function
      graph hook function and the management of the shadow stack, simplifying the
      work done in the architecture dependent prepare_ftrace_return().
      
      Have ARM use the new code, and remove the shadow stack management as well as
      having to set up the trace structure.
      
      This is needed to prepare for a fix of a design bug on how the curr_ret_stack
      is used.
      
      Cc: Russell King <linux@armlinux.org.uk>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: stable@kernel.org
      Fixes: 03274a3f ("tracing/fgraph: Adjust fgraph depth before calling trace return callback")
      Reviewed-by: NMasami Hiramatsu <mhiramat@kernel.org>
      Signed-off-by: NSteven Rostedt (VMware) <rostedt@goodmis.org>
      f1f5b14a
  7. 27 11月, 2018 3 次提交
  8. 26 11月, 2018 8 次提交
  9. 21 11月, 2018 1 次提交
  10. 19 11月, 2018 2 次提交
  11. 14 11月, 2018 1 次提交
    • C
      ARM: dts: sun8i: a83t: bananapi-m3: increase vcc-pd voltage to 3.3V · 5f8208f5
      Corentin Labbe 提交于
      Since commit d7c5f686 ("ARM: dts: sun8i: a83t: bananapi-m3: Add
      AXP813 regulator nodes") my BPIM3 no longer works at gigabit speed.
      
      With the default setting, dldo3 is regulated at 2.9v which seems
      sufficient for the PHY but the aforementioned commit drops it to 2.5V
      which is insufficient. Note that this behaviour is random for all BPIM3.
      Some work with 2.5V, but some don't.
      
      Finnaly, someone from Bananapi confirmed that this regulator must be set
      to 3.3V.
      
      Fixes: d7c5f686 ("ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813
      		      regulator nodes")
      Signed-off-by: NCorentin Labbe <clabbe@baylibre.com>
      [wens@csie.org: Reworked commit message]
      Signed-off-by: NChen-Yu Tsai <wens@csie.org>
      5f8208f5
  12. 12 11月, 2018 7 次提交
  13. 09 11月, 2018 5 次提交
  14. 08 11月, 2018 1 次提交