1. 01 10月, 2021 1 次提交
  2. 20 8月, 2021 2 次提交
  3. 19 8月, 2021 3 次提交
  4. 18 8月, 2021 3 次提交
  5. 11 8月, 2021 1 次提交
  6. 04 8月, 2021 1 次提交
  7. 30 7月, 2021 1 次提交
  8. 22 6月, 2021 2 次提交
  9. 18 6月, 2021 1 次提交
  10. 11 6月, 2021 1 次提交
  11. 27 5月, 2021 1 次提交
  12. 26 5月, 2021 1 次提交
    • F
      arm64: Rename arm64-internal cache maintenance functions · fade9c2c
      Fuad Tabba 提交于
      Although naming across the codebase isn't that consistent, it
      tends to follow certain patterns. Moreover, the term "flush"
      isn't defined in the Arm Architecture reference manual, and might
      be interpreted to mean clean, invalidate, or both for a cache.
      
      Rename arm64-internal functions to make the naming internally
      consistent, as well as making it consistent with the Arm ARM, by
      specifying whether it applies to the instruction, data, or both
      caches, whether the operation is a clean, invalidate, or both.
      Also specify which point the operation applies to, i.e., to the
      point of unification (PoU), coherency (PoC), or persistence
      (PoP).
      
      This commit applies the following sed transformation to all files
      under arch/arm64:
      
      "s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\
      "s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\
      "s/\binvalidate_icache_range\b/icache_inval_pou/g;"\
      "s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\
      "s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\
      "s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\
      "s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\
      "s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\
      "s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\
      "s/\b__flush_icache_all\b/icache_inval_all_pou/g;"
      
      Note that __clean_dcache_area_poc is deliberately missing a word
      boundary check at the beginning in order to match the efistub
      symbols in image-vars.h.
      
      Also note that, despite its name, __flush_icache_range operates
      on both instruction and data caches. The name change here
      reflects that.
      
      No functional change intended.
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NFuad Tabba <tabba@google.com>
      Reviewed-by: NArd Biesheuvel <ardb@kernel.org>
      Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.comSigned-off-by: NWill Deacon <will@kernel.org>
      fade9c2c
  13. 15 5月, 2021 1 次提交
  14. 17 4月, 2021 2 次提交
  15. 07 4月, 2021 3 次提交
  16. 06 4月, 2021 1 次提交
  17. 31 3月, 2021 1 次提交
  18. 25 3月, 2021 1 次提交
  19. 19 3月, 2021 7 次提交
  20. 18 3月, 2021 1 次提交
  21. 10 3月, 2021 1 次提交
    • M
      KVM: arm64: Ensure I-cache isolation between vcpus of a same VM · 01dc9262
      Marc Zyngier 提交于
      It recently became apparent that the ARMv8 architecture has interesting
      rules regarding attributes being used when fetching instructions
      if the MMU is off at Stage-1.
      
      In this situation, the CPU is allowed to fetch from the PoC and
      allocate into the I-cache (unless the memory is mapped with
      the XN attribute at Stage-2).
      
      If we transpose this to vcpus sharing a single physical CPU,
      it is possible for a vcpu running with its MMU off to influence
      another vcpu running with its MMU on, as the latter is expected to
      fetch from the PoU (and self-patching code doesn't flush below that
      level).
      
      In order to solve this, reuse the vcpu-private TLB invalidation
      code to apply the same policy to the I-cache, nuking it every time
      the vcpu runs on a physical CPU that ran another vcpu of the same
      VM in the past.
      
      This involve renaming __kvm_tlb_flush_local_vmid() to
      __kvm_flush_cpu_context(), and inserting a local i-cache invalidation
      there.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NMarc Zyngier <maz@kernel.org>
      Acked-by: NWill Deacon <will@kernel.org>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Link: https://lore.kernel.org/r/20210303164505.68492-1-maz@kernel.org
      01dc9262
  22. 09 2月, 2021 1 次提交
  23. 23 1月, 2021 1 次提交
  24. 21 1月, 2021 1 次提交
  25. 30 12月, 2020 1 次提交