Skip to content

K
Kernel

openeuler / Kernel
接近 2 年 前同步成功

通知 8
Star 0
Fork 0
K
Kernel
切换分支/标签
  1. 29 11月, 2018 2 次提交
  3. 07 10月, 2018 1 次提交
  5. 23 4月, 2018 1 次提交
  7. 29 11月, 2017 1 次提交
  9. 22 8月, 2017 1 次提交
  11. 08 12月, 2016 1 次提交
  13. 08 8月, 2016 1 次提交
  15. 16 11月, 2015 1 次提交
  17. 29 10月, 2015 2 次提交
  19. 26 8月, 2015 1 次提交
  21. 31 7月, 2015 1 次提交
    • C
      dmaengine: at_hdmac: fix residue computation · 93dce3a6
      由 Cyrille Pitchen 提交于 
      As claimed by the programmer datasheet and confirmed by the IP designer,
the Block Transfer Size (BTSIZE) bitfield of the Channel x Control A
Register (CTRLAx) always refers to a number of Source Width (SRC_WIDTH)
transfers.

Both the SRC_WIDTH and BTSIZE bitfields can be extacted from the CTRLAx
register to compute the DMA residue. So the 'tx_width' field is useless
and can be removed from the struct at_desc.

Before this patch, atc_prep_slave_sg() was not consistent: BTSIZE was
correctly initialized according to the SRC_WIDTH but 'tx_width' was always
set to reg_width, which was incorrect for MEM_TO_DEV transfers. It led to
bad DMA residue when 'tx_width' != SRC_WIDTH.

Also the 'tx_width' field was mostly set only in the first and last
descriptors. Depending on the kind of DMA transfer, this field remained
uninitialized for intermediate descriptors. The accurate DMA residue was
computed only when the currently processed descriptor was the first or the
last of the chain. This algorithm was a little bit odd. An accurate DMA
residue can always be computed using the SRC_WIDTH and BTSIZE bitfields
in the CTRLAx register.

Finally, the test to check whether the currently processed descriptor is
the last of the chain was wrong: for cyclic transfer, last_desc->lli.dscr
is NOT equal to zero, since set_desc_eol() is never called, but logically
equal to first_desc->txd.phys. This bug has a side effect on the
drivers/tty/serial/atmel_serial.c driver, which uses cyclic DMA transfer
to receive data. Since the DMA residue was wrong each time the DMA
transfer reaches the second (and last) period of the transfer, no more
data were received by the USART driver till the cyclic DMA transfer loops
back to the first period.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NTorsten Fleischer <torfl6749@gmail.com>
Tested-by: NJirí Prchal <jiri.prchal@aksignal.cz>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      93dce3a6
  23. 07 7月, 2015 1 次提交
  25. 12 6月, 2015 1 次提交
  27. 13 3月, 2015 2 次提交
    • T
      dmaengine: at_hdmac: Fix calculation of the residual bytes · bdf6c792
      由 Torsten Fleischer 提交于 
      This patch fixes the following issues regarding to the calculation of the
residue:

1. The residue is always calculated for the current transfer even if the
cookie is associated to a pending transfer.

2. For scatter/gather DMA the calculation of the residue for the current
transfer doesn't include the bytes of the child descriptors that are already
transferred.
It only calculates the difference between the transfer's total length minus
the number of bytes that are already transferred for the current child
descriptor.
For example: There is a scatter/gather DMA transfer with a total length of
1 MByte. Getting the residue several times while the transfer is running shows
something like that:

1: residue = 975584
2: residue = 1002766
3: residue = 992627
4: residue = 983767
5: residue = 985694
6: residue = 1008094
7: residue = 1009741
8: residue = 1011195

3. The driver stores the residue but never resets it when starting a new
transfer.
For example: If there are two subsequent DMA transfers. The first one with
a total length of 1 MByte and the second one with a total length of 1 kByte.
Getting the residue for both transfers shows something like that:

transfer 1: residue = 975584
transfer 2: residue = 1048380

Changes from V1:
   * Fixed coding style of the multi-line comments.
   * Improved accuracy of the residue calculation when the transfer for the
     first descriptor is active.

Changes from V2:
   * Member 'tx_width' of 'struct at_desc' restored, because the transfer width
     can't be derived from the source width when using "slave_sg".
     The transfer width is needed for the calculation of the residue if either
     the transfer of the first or the last descriptor is in progress.
     In the case of a "memory_to_memory_sg" transfer (part of this patch
     series) the transfer width of both descriptors may differ. Thus it is
     required to additionally set 'tx_width' of the last descriptor.
   * Added functions for multiply used calculations.
Signed-off-by: NTorsten Fleischer <torfl6749@gmail.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      bdf6c792
    • T
      dmaengine: at_hdmac: Add support for memory to memory sg transfers · 265567fb
      由 Torsten Fleischer 提交于 
      This patch adds support for memory to memory scatter-gather transfers.

Changes from V1:
   * Fixed coding style of the multi-line comments.

Changes from V2:
   * Added setup of 'desc->tx_width' that is needed to calculate the
     residue.
Signed-off-by: NTorsten Fleischer <torfl6749@gmail.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      265567fb
  29. 14 1月, 2015 1 次提交
  31. 22 12月, 2014 1 次提交
  33. 08 8月, 2014 1 次提交
  35. 04 8月, 2014 1 次提交
  37. 17 3月, 2014 1 次提交
  39. 15 11月, 2013 1 次提交
  41. 14 11月, 2013 1 次提交
  43. 25 10月, 2013 1 次提交
  45. 05 7月, 2013 10 次提交
  47. 30 4月, 2013 1 次提交
  49. 18 4月, 2013 1 次提交
  51. 15 4月, 2013 1 次提交
  53. 12 1月, 2013 1 次提交
  55. 22 9月, 2012 1 次提交