Skip to content

K
Kernel

openeuler / Kernel
接近 2 年 前同步成功

通知 8
Star 0
Fork 0
K
Kernel
切换分支/标签
  1. 31 5月, 2018 3 次提交
  3. 30 5月, 2018 2 次提交
  5. 29 5月, 2018 4 次提交
  7. 28 5月, 2018 1 次提交
  9. 21 5月, 2018 11 次提交
  11. 08 5月, 2018 4 次提交
  13. 03 5月, 2018 12 次提交
  15. 02 5月, 2018 3 次提交
    • C
      mmc: mediatek: add 64G DRAM DMA support · 2a9bde19
      由 Chaotian Jing 提交于 
      MT2712 MSDC supports 64G DRAM DMA access, it needs update
gpd/bd structure.
Signed-off-by: NChaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      2a9bde19
    • T
      mmc: mmci: Remove bogus local_irq_save() · 99d02d6c
      由 Thomas Gleixner 提交于 
      On !RT interrupt runs with interrupts disabled. On RT it's in a
thread, so no need to disable interrupts at all.
Remove the local_irq_save() invocation.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      99d02d6c
    • A
      mmc: sdhci-esdhc-imx: Set maximum watermark levels for PIO access · 3fbd4322
      由 Andrew Gabbasov 提交于 
      While performing R/W access in PIO mode, the common SDHCI driver checks
the buffer ready status once per whole block processing. That is, after
getting an appropriate interrupt, or checking an appropriate status bit,
the driver makes buffer accesses for the whole block size (e.g. 128 reads
for 512 bytes block). This is done in accordance with SD Host Controller
Specification.

At the same time, the Ultra Secured Digital Host Controller (uSDHC), used
in i.MX6 (and, probably, earlier i.MX series too), uses a separate
Watermark Levels register, controlling the amount of data or space
available when raising status bit or interrupt. For default watermark
setting of 16 words, the controller expects (and guarantees) no more
than 16 buffer accesses after raising buffer ready status bit and
generating an appropriate interrupt. If the driver tries to access the
whole block size, it will get incorrect data at the end, and a new
interrupt will appear later, when the driver already doesn't expect it.
This happens sometimes, more likely on low frequencies, e.g. when
reading EXT_CSD at MMC card initialization phase
(which makes that initialization fail).

Such behavior of i.MX uSDHC seems to be non-compliant
to SDHCI Specification, but this is the way it works now.

In order not to rewrite the SDHCI driver PIO mode access logic,
the IMX specific driver can just set the watermark level to default
block size (128 words or 512 bytes), so that the controller behavior
will be consistent to generic specification. This patch does this
for PIO mode accesses only, restoring default values for DMA accesses
to avoid any possible side effects from performance point of view.
Signed-off-by: NAndrew Gabbasov <andrew_gabbasov@mentor.com>
Signed-off-by: NHarish Jenny K N <harish_kandiga@mentor.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      3fbd4322