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  1. 18 7月, 2022 1 次提交
  3. 01 5月, 2022 1 次提交
  5. 30 11月, 2021 1 次提交
    • B
      net: stmmac: Add platform level debug register dump feature · 4047b9db
      由 Bhupesh Sharma 提交于 
      dwmac-qcom-ethqos currently exposes a mechanism to dump rgmii registers
after the 'stmmac_dvr_probe()' returns. However with commit
5ec55823 ("net: stmmac: add clocks management for gmac driver"),
we now let 'pm_runtime_put()' disable the clocks before returning from
'stmmac_dvr_probe()'.

This causes a crash when 'rgmii_dump()' register dumps are enabled,
as the clocks are already off.

Since other dwmac drivers (possible future users as well) might
require a similar register dump feature, introduce a platform level
callback to allow the same.

This fixes the crash noticed while enabling rgmii_dump() dumps in
dwmac-qcom-ethqos driver as well. It also allows future changes
to keep a invoking the register dump callback from the correct
place inside 'stmmac_dvr_probe()'.

Fixes: 5ec55823 ("net: stmmac: add clocks management for gmac driver")
Cc: Joakim Zhang <qiangqing.zhang@nxp.com>
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4047b9db
  7. 24 11月, 2021 1 次提交
  9. 06 7月, 2021 2 次提交
  11. 30 6月, 2021 1 次提交
    • L
      net: stmmac: option to enable PHY WOL with PMT enabled · 5a9b876e
      由 Ling Pei Lee 提交于 
      The current stmmac driver WOL implementation will enable MAC WOL
if MAC HW PMT feature is on. Else, the driver will check for
PHY WOL support. There is another case where MAC HW PMT is
enabled but the platform still goes for the PHY WOL option.
E.g, Intel platform are designed for PHY WOL but not MAC WOL
although HW MAC PMT features are enabled.

Introduce use_phy_wol platform data to select PHY WOL
instead of depending on HW PMT features. Set use_phy_wol
will disable the plat->pmt which currently used to
determine the system to wake up by MAC WOL or PHY WOL.
Signed-off-by: NLing Pei Lee <pei.lee.ling@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5a9b876e
  13. 09 6月, 2021 2 次提交
    • M
      net: stmmac: explicitly deassert GMAC_AHB_RESET · e67f325e
      由 Matthew Hagan 提交于 
      We are currently assuming that GMAC_AHB_RESET will already be deasserted
by the bootloader. However if this has not been done, probing of the GMAC
will fail. To remedy this we must ensure GMAC_AHB_RESET has been deasserted
prior to probing.

v2 changes:
 - remove NULL condition check for stmmac_ahb_rst in stmmac_main.c
 - unwrap dev_err() message in stmmac_main.c
 - add PTR_ERR() around plat->stmmac_ahb_rst in stmmac_platform.c

v3 changes:
 - add error pointer to dev_err() output
 - add reset_control_assert(stmmac_ahb_rst) in stmmac_dvr_remove
 - revert PTR_ERR() around plat->stmmac_ahb_rst since this is performed
   on the returned value of ret by the calling function
Signed-off-by: NMatthew Hagan <mnhagan88@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e67f325e
    • V
      net: stmmac: enable Intel mGbE 2.5Gbps link speed · 46682cb8
      由 Voon Weifeng 提交于 
      The Intel mGbE supports 2.5Gbps link speed by increasing the clock rate by
2.5 times of the original rate. In this mode, the serdes/PHY operates at a
serial baud rate of 3.125 Gbps and the PCS data path and GMII interface of
the MAC operate at 312.5 MHz instead of 125 MHz.

For Intel mGbE, the overclocking of 2.5 times clock rate to support 2.5G is
only able to be configured in the BIOS during boot time. Kernel driver has
no access to modify the clock rate for 1Gbps/2.5G mode. The way to
determined the current 1G/2.5G mode is by reading a dedicated adhoc
register through mdio bus. In short, after the system boot up, it is either
in 1G mode or 2.5G mode which not able to be changed on the fly.

Compared to 1G mode, the 2.5G mode selects the 2500BASEX as PHY interface and
disables the xpcs_an_inband. This is to cater for some PHYs that only
supports 2500BASEX PHY interface with no autonegotiation.

v2: remove MAC supported link speed masking
v3: Restructure  to introduce intel_speed_mode_2500() to read serdes registers
    for max speed supported and select the appropritate configuration.
    Use max_speed to determine the supported link speed mask.
Signed-off-by: NVoon Weifeng <weifeng.voon@intel.com>
Signed-off-by: NMichael Sit Wei Hong <michael.wei.hong.sit@intel.com>
Reviewed-by: NVladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      46682cb8
  15. 02 6月, 2021 1 次提交
  17. 18 5月, 2021 1 次提交
  19. 23 4月, 2021 1 次提交
  21. 15 4月, 2021 1 次提交
  23. 26 3月, 2021 2 次提交
  25. 25 3月, 2021 2 次提交
  27. 19 3月, 2021 1 次提交
  29. 16 3月, 2021 2 次提交
  31. 18 2月, 2021 1 次提交
  33. 09 12月, 2020 1 次提交
  35. 29 9月, 2020 1 次提交
  37. 26 9月, 2020 1 次提交
  39. 22 4月, 2020 1 次提交
    • V
      net: stmmac: Enable SERDES power up/down sequence · b9663b7c
      由 Voon Weifeng 提交于 
      This patch is to enable Intel SERDES power up/down sequence. The SERDES
converts 8/10 bits data to SGMII signal. Below is an example of
HW configuration for SGMII mode. The SERDES is located in the PHY IF
in the diagram below.

<-----------------GBE Controller---------->|<--External PHY chip-->
+----------+         +----+            +---+           +----------+
|   EQoS   | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | External |
|   MAC    |         |xPCS|            |IF |           | PHY      |
+----------+         +----+            +---+           +----------+
       ^               ^                 ^                ^
       |               |                 |                |
       +---------------------MDIO-------------------------+

PHY IF configuration and status registers are accessible through
mdio address 0x15 which is defined as mdio_adhoc_addr. During D0,
The driver will need to power up PHY IF by changing the power state
to P0. Likewise, for D3, the driver sets PHY IF power state to P3.
Signed-off-by: NVoon Weifeng <weifeng.voon@intel.com>
Signed-off-by: NOng Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b9663b7c
  41. 10 3月, 2020 1 次提交
  43. 14 1月, 2020 1 次提交
  45. 19 12月, 2019 1 次提交
  47. 05 11月, 2019 1 次提交
    • A
      net: of_get_phy_mode: Change API to solve int/unit warnings · 0c65b2b9
      由 Andrew Lunn 提交于 
      Before this change of_get_phy_mode() returned an enum,
phy_interface_t. On error, -ENODEV etc, is returned. If the result of
the function is stored in a variable of type phy_interface_t, and the
compiler has decided to represent this as an unsigned int, comparision
with -ENODEV etc, is a signed vs unsigned comparision.

Fix this problem by changing the API. Make the function return an
error, or 0 on success, and pass a pointer, of type phy_interface_t,
where the phy mode should be stored.

v2:
Return with *interface set to PHY_INTERFACE_MODE_NA on error.
Add error checks to all users of of_get_phy_mode()
Fixup a few reverse christmas tree errors
Fixup a few slightly malformed reverse christmas trees

v3:
Fix 0-day reported errors.
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0c65b2b9
  49. 04 10月, 2019 1 次提交
  51. 11 9月, 2019 1 次提交
    • A
      net: stmmac: implement support for passive mode converters via dt · 0060c878
      由 Alexandru Ardelean 提交于 
      In-between the MAC & PHY there can be a mode converter, which converts one
mode to another (e.g. GMII-to-RGMII).

The converter, can be passive (i.e. no driver or OS/SW information
required), so the MAC & PHY need to be configured differently.

For the `stmmac` driver, this is implemented via a `mac-mode` property in
the device-tree, which configures the MAC into a certain mode, and for the
PHY a `phy_interface` field will hold the mode of the PHY. The mode of the
PHY will be passed to the PHY and from there-on it work in a different
mode. If unspecified, the default `phy-mode` will be used for both.
Signed-off-by: NAlexandru Ardelean <alexandru.ardelean@analog.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0060c878
  53. 28 8月, 2019 1 次提交
  55. 09 8月, 2019 1 次提交
  57. 28 7月, 2019 1 次提交
    • T
      net: stmmac: Make MDIO bus reset optional · 1a981c05
      由 Thierry Reding 提交于 
      The Tegra EQOS driver already resets the MDIO bus at probe time via the
reset GPIO specified in the phy-reset-gpios device tree property. There
is no need to reset the bus again later on.

This avoids the need to query the device tree for the snps,reset GPIO,
which is not part of the Tegra EQOS device tree bindings. This quiesces
an error message from the generic bus reset code if it doesn't find the
snps,reset related delays.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1a981c05
  59. 17 6月, 2019 3 次提交
  61. 16 6月, 2019 1 次提交
  63. 15 6月, 2019 1 次提交
  65. 05 6月, 2019 1 次提交