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  1. 12 1月, 2015 9 次提交
  3. 27 12月, 2014 1 次提交
  5. 24 12月, 2014 1 次提交
  7. 23 12月, 2014 2 次提交
  9. 22 12月, 2014 2 次提交
  11. 20 12月, 2014 4 次提交
  13. 19 12月, 2014 12 次提交
  15. 18 12月, 2014 9 次提交
    • F
      watchdog: imx2_wdt: Fix the argument of watchdog_active() · ba90f261
      由 Fabio Estevam 提交于 
      Fix the following build warning by passing the expected argument type to
watchdog_active():

drivers/watchdog/imx2_wdt.c: In function 'imx2_wdt_suspend':
drivers/watchdog/imx2_wdt.c:340:2: warning: passing argument 1 of 'watchdog_active' from incompatible pointer type [enabled by default]
In file included from drivers/watchdog/imx2_wdt.c:38:0:
include/linux/watchdog.h:104:20: note: expected 'struct watchdog_device *' but argument is of type 'struct watchdog_device **'
Reported-by: NOlof's autobuilder <build@lixom.net>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      ba90f261
    • X
      watchdog: imx2_wdt: Add power management support. · aefbaf3a
      由 Xiubo Li 提交于 
      Add power management operations(suspend and resume) as part of
dev_pm_ops for IMX2 watchdog driver.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      aefbaf3a
    • G
      i2c: sh_mobile: I2C_SH_MOBILE should depend on HAS_DMA · f16ea4f0
      由 Geert Uytterhoeven 提交于 
      If NO_DMA=y:

drivers/built-in.o: In function `sh_mobile_i2c_dma_unmap':
i2c-sh_mobile.c:(.text+0x60de42): undefined reference to `dma_unmap_single'
drivers/built-in.o: In function `sh_mobile_i2c_xfer_dma':
i2c-sh_mobile.c:(.text+0x60df22): undefined reference to `dma_map_single'
i2c-sh_mobile.c:(.text+0x60df2e): undefined reference to `dma_mapping_error'
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      f16ea4f0
    • W
      i2c: sh_mobile: rework deferred probing · 55f5f986
      由 Wolfram Sang 提交于 
      DMA is opt-in for this driver. So, we can't use deferred probing for
requesting DMA channels in probe, because our driver would get endlessly
deferred if DMA support is compiled in AND the DMA driver is missing.
Because we can't know when the DMA driver might show up, we always try
again when a DMA transfer would be possible. The downside is that there
is more overhead for setting up PIO transfers under the above scenario.
But well, having DMA enabled and the proper DMA driver missing looks
like a broken or test config anyhow.
Reported-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      55f5f986
    • W
      i2c: sh_mobile: refactor DMA setup · e844a799
      由 Wolfram Sang 提交于 
      Refactor DMA setup to keep the errno so we can implement better
deferred probe support in the next step.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      e844a799
    • T
      i2c: mv64xxx: rework offload support to fix several problems · 00d8689b
      由 Thomas Petazzoni 提交于 
      Originally, the I2C controller supported by the i2c-mv64xxx driver
requires a lot of software support: an interrupt is generated at each
step of an I2C transaction (after the start bit, after sending the
address, etc.) and the driver is in charge of re-programming the I2C
controller to do the next step of the I2C transaction. This explains
the fairly complex state machine that the driver has.

On Marvell Armada XP and later processors (Armada 375, 38x, etc.), the
I2C controller was extended with a part called the "I2C Bridge", which
allows to offload the I2C transaction completely to the
hardware. Initial support for this mechanism was added in commit
930ab3d4 ("i2c: mv64xxx: Add I2C Transaction Generator support").

However, the implementation done in this commit has two related
issues, which this commit fixes by completely changing how the offload
implementation is done:

 * SMBus read transfers, where there is one write to select the
   register immediately followed in the same transaction by one read,
   were making the processor hang. This was easier visible on the
   Marvell Armada XP WRT1900AC platform using a driver for an I2C LED
   controller, or on other Armada XP platforms by using a simple
   'i2cget' command to read an I2C EEPROM.

 * The implementation was based on the fact that the offload engine
   was re-programmed to transfer each message of an I2C xfer: this
   meant that each message sent with the offload engine was starting
   with a normal I2C start sequence. However, the I2C subsystem
   assumes that all messages belonging to the same xfer will use the
   so-called "repeated start" so that the entire I2C xfer is seen as
   one transfer by the I2C devices and cannot be interrupt by other
   I2C masters on the same bus.

In fact, the "I2C Bridge" allows to offload three types of xfer:

 - xfer of one write message
 - xfer of one read message
 - xfer of one write message followed by one read message

For all other situations, we have to fallback to not using the "I2C
Bridge" in order to get proper I2C semantics.

Therefore, this commit reworks the offload implementation to put it
not at the message level, but at the xfer level: in the
mv64xxx_i2c_xfer() function, we decide if the transaction can be
offloaded (in which case it is handled by the
mv64xxx_i2c_offload_xfer() function), or otherwise it is handled by
the slow path (implemented in the existing mv64xxx_i2c_execute_msg()).

This allows to simplify the state machine, which no longer needs to
have any state related to the offload implementation: the offload
implementation is now completely separated from the slow path (with
the exception of the interrupt handler, of course).

In summary:

 - mv64xxx_i2c_can_offload() will analyze an I2C xfer and decided of
   the "I2C Bridge" can be used to offload it or not.

 - mv64xxx_i2c_offload_xfer() will actually program the "I2C Bridge"
   to offload one xfer (of either one or two messages), and block
   using mv64xxx_i2c_wait_for_completion() until the xfer completes.

 - The interrupt handler mv64xxx_i2c_intr() is modified to push the
   offload related code to a separate function,
   mv64xxx_i2c_intr_offload(). It will take care of reading the
   received data if needed.

This commit was tested on:

 - Armada XP OpenBlocks AX3-4 (EEPROM on I2C and RTC on I2C)
 - Armada XP WRT1900AC (LED controller on I2C)
 - Armada XP GP (EEPROM on I2C)

Fixes: 930ab3d4 ("i2c: mv64xxx: Add I2C Transaction Generator support")
Cc: <stable@vger.kernel.org> # v3.12+
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
[wsa: fixed checkpatch warnings]
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      00d8689b
    • T
      i2c: mv64xxx: use BIT() macro for register value definitions · 12598695
      由 Thomas Petazzoni 提交于 
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      12598695
    • R
      drm/atomic: fix potential null ptr on plane enable · 4b08eae5
      由 Rob Clark 提交于 
      When a plane is being enabled, plane->crtc has not been set yet.  Use
plane->state->crtc.
Signed-off-by: NRob Clark <robdclark@gmail.com>
Reviewed-by: NSean Paul <seanpaul@chromium.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      4b08eae5
    • Z
      dm: fix missed error code if .end_io isn't implemented by target_type · 5164bece
      由 zhendong chen 提交于 
      In bio-based DM's clone_endio(), when target_type doesn't implement
.end_io (e.g. linear) r will be always be initialized 0.  So if a
WRITE SAME bio fails WRITE SAME will not be disabled as intended.

Fix this by initializing r to error, rather than 0, in clone_endio().
Signed-off-by: NAlex Chen <alex.chen@huawei.com>
Signed-off-by: NMike Snitzer <snitzer@redhat.com>
Fixes: 7eee4ae2 ("dm: disable WRITE SAME if it fails")
Cc: stable@vger.kernel.org
      5164bece