pci-mvebu.c uses irq_domain_add_linear() and related interfaces but relies
on <linux/irqdomain.h> but doesn't include it directly; it relies on the
fact that <linux/of_irq.h> includes it.

Include <linux/irqdomain.h> directly to remove this implicit dependency.

Link: https://lore.kernel.org/r/20221031153954.1163623-4-helgaas@kernel.orgSigned-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>

pcie-microchip-host.c uses irq_domain_add_linear() and related interfaces,
so it needs <linux/irqdomain.h> but doesn't include it directly; it relies
on the fact that <linux/of_irq.h> includes it.

But pcie-microchip-host.c *doesn't* need <linux/of_irq.h> itself.  Include
<linux/irqdomain.h> directly to remove this implicit dependency so a future
patch can drop <linux/of_irq.h>.

Link: https://lore.kernel.org/r/20221031153954.1163623-3-helgaas@kernel.orgSigned-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NConor Dooley <conor.dooley@microchip.com>

pcie-altera-msi.c uses irq_domain_add_linear() and related interfaces, so
it needs <linux/irqdomain.h> but doesn't include it directly; it relies on
the fact that <linux/of_irq.h> includes it.

But pcie-altera-msi.c *doesn't* need <linux/of_irq.h> itself.  Include
<linux/irqdomain.h> directly to remove this implicit dependency so a future
patch can drop <linux/of_irq.h>.

Link: https://lore.kernel.org/r/20221031153954.1163623-2-helgaas@kernel.orgSigned-off-by: NBjorn Helgaas <bhelgaas@google.com>

If platform_get_resource_byname() fails, 'mmio_res' will be set to NULL
pointer, which causes a NULL pointer dereference when it is used in
qcom_pcie_perst_deassert().

Check the return value to prevent it.

Link: https://lore.kernel.org/r/20220429080740.1294797-1-yangyingliang@huawei.com
Fixes: f55fee56 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver")
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NAndrew Halaney <ahalaney@redhat.com>

Add support for SM8450 SoC to the Qualcomm PCIe Endpoint Controller
driver. The driver uses the same config as the existing SDX55 chipset,
so additional settings are not required.

Link: https://lore.kernel.org/r/20220914075350.7992-13-manivannan.sadhasivam@linaro.orgSigned-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

PERST separation is an optional debug feature used to collect the crash
dump from the PCIe endpoint devices by the PCIe host when the endpoint
crashes. This feature keeps the PCIe link up by separating the PCIe IP
block from the SoC reset logic.

Make the property optional in the driver.

Link: https://lore.kernel.org/r/20220914075350.7992-10-manivannan.sadhasivam@linaro.orgSigned-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The Master AXI clock can be disabled when it is not used i.e., when there
is no traffic on the PCIe bus. This helps to save power during idle state.

[bhelgaas: tidy and wrap comment]
Link: https://lore.kernel.org/r/20220914075350.7992-8-manivannan.sadhasivam@linaro.orgSigned-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

During L1SS, gate the Master clock supplied to the MHI bus to save power.

Link: https://lore.kernel.org/r/20220914075350.7992-7-manivannan.sadhasivam@linaro.orgSigned-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Qualcomm PCIe controllers have debug registers in the MMIO region
that count PCIe link transitions. Expose them over debugfs to
userspace to help debug the low power issues.

Link: https://lore.kernel.org/r/20220914075350.7992-6-manivannan.sadhasivam@linaro.orgSigned-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Disable the Global and PERST IRQs during driver remove to avoid getting
spurious IRQs after resource deallocation.

Link: https://lore.kernel.org/r/20220914075350.7992-5-manivannan.sadhasivam@linaro.orgSigned-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

In the qcom_pcie_ep_get_resources() function, dev pointer is already
cached in a local variable. So let's make use of it instead of getting
the dev pointer again from pdev struct.

Link: https://lore.kernel.org/r/20220914075350.7992-4-manivannan.sadhasivam@linaro.orgSigned-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Generally, device drivers should just rely on the platform data like
devicetree to supply the clocks required for the functioning of the
peripheral. There is no need to hardcode the clk info in the driver.
So get rid of the static clk info and obtain the platform supplied
clks.

The total number of clocks supplied is obtained using the
devm_clk_bulk_get_all() API and used for the rest of the clk_bulk_ APIs.

Link: https://lore.kernel.org/r/20220914075350.7992-3-manivannan.sadhasivam@linaro.orgSigned-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Add kernel-doc for qcom_pcie_ep structure.

Link: https://lore.kernel.org/r/20220914075350.7992-2-manivannan.sadhasivam@linaro.orgSigned-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Refer to phy_core driver, phy_init() must be called before phy_power_on().
Fix the wrong order of phy_init() and phy_power_on() here.

Link: https://lore.kernel.org/r/1662344583-18874-1-git-send-email-hongxing.zhu@nxp.com
Fixes: 1aa97b00 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver")
Tested-by: NAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: NRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NVinod Koul <vkoul@kernel.org>
Acked-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Add i.MX8MP PCIe support.
To avoid codes duplication when find the syscon regmap, add the iomux
gpr syscon compatible into drvdata.

Link: https://lore.kernel.org/r/1662109086-15881-8-git-send-email-hongxing.zhu@nxp.comTested-by: NMarek Vasut <marex@denx.de>
Tested-by: NRichard Leitner <richard.leitner@skidata.com>
Tested-by: NAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: NRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NLucas Stach <l.stach@pengutronix.de>

As a preparation to unexport of_gpio_named_count(), convert the
driver to use gpiod_count() instead.

Link: https://lore.kernel.org/r/20220830183310.48541-1-andriy.shevchenko@linux.intel.comSigned-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>

Simplify pci-tegra.c driver code and use new PCI_CONF1_EXT_ADDRESS() macro
for accessing PCI config space.

Link: https://lore.kernel.org/r/20220928121911.14994-1-pali@kernel.orgSigned-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NThierry Reding <treding@nvidia.com>

Use a more descriptive name for the reset host-init error label for
consistency.

Link: https://lore.kernel.org/r/20220928155421.21660-3-johan+linaro@kernel.orgSigned-off-by: NJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Drop the unused and confusingly named post_deinit callback that was
added for the now removed pipe clock handling.

If ever needed we can add back a callback named pre_deinit (or perhaps
rather pre_phy_power_off) instead.

Link: https://lore.kernel.org/r/20220928155421.21660-2-johan+linaro@kernel.orgSigned-off-by: NJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Simplify pcie-mt7621.c driver code and use new PCI_CONF1_EXT_ADDRESS()
macro for accessing PCIe config space.

Link: https://lore.kernel.org/r/20220924092404.31776-4-pali@kernel.orgSigned-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: NSergio Paracuellos <sergio.paracuellos@gmail.com>

Simplify pci-ftpci100.c driver code and use new PCI_CONF1_ADDRESS() macro
for accessing PCI config space.

Link: https://lore.kernel.org/r/20220924092404.31776-3-pali@kernel.orgSigned-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Register with Subsystem Device/Vendor ID is at offset 0x2c.

Export it via the emulated bridge to enable support for the Subsystem
Device/Vendor ID - by reading it in the PCI controller config space and
storing it in the emulated bridge control structures, so that it is
exposed in the respective PCI capability.

After this change Subsystem ID is visible in lspci output at line:

  Capabilities: [40] Subsystem

Link: https://lore.kernel.org/r/20220711225915.13896-1-pali@kernel.orgSigned-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

The driver allocates reset GPIO in apple_pcie_setup_port() but neither
releases the resource, nor uses devm API to have it released
automatically.

Let's fix this by switching to devm API. While at it let's use generic
devm_fwnode_gpiod_get() instead of OF-specific gpiod_get_from_of_node()
- this will allow us top stop exporting the latter down the road.

Link: https://lore.kernel.org/r/YxatO5OaI2RpxQ2M@google.com
Fixes: 1e33888f ("PCI: apple: Add initial hardware bring-up")
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NHector Martin <marcan@marcan.st>
Acked-by: NMarc Zyngier <maz@kernel.org>

Add MODULE_DEVICE_TABLE to enable module autoloading for respective
device.

Link: https://lore.kernel.org/r/20220430084740.3769925-1-dmitry.baryshkov@linaro.org
Fixes: f55fee56 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver")
Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Re-work the msi_msg DMA allocation logic to use dmam_alloc_coherent() which
uses the coherent DMA mask to try to return an allocation within the DMA
mask limits. With that, we now can drop the msi_page parameter in struct
dw_pcie_rp. This allows kernel configurations that disable ZONE_DMA32 to
continue supporting a 32-bit DMA mask. Without this patch, the PCIe host
device will fail to probe when ZONE_DMA32 is disabled.

Link: https://lore.kernel.org/r/20220825235404.4132818-2-willmcvicker@google.com
Fixes: 35797e67 ("PCI: dwc: Fix MSI msi_msg DMA mapping")
Reported-by: NIsaac J. Manjarres <isaacmanjarres@google.com>
Signed-off-by: NWill McVicker <willmcvicker@google.com>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Acked-by: NJingoo Han <jingoohan1@gmail.com>

mvebu and aardvark HW have PCIe capabilities on different offset in PCI
config space. Extend pci-bridge-emul.c code to allow setting custom driver
custom value where PCIe capabilities starts.

With this change PCIe capabilities of both drivers are reported at the same
location as where they are reported by U-Boot - in their real HW offset.

Link: https://lore.kernel.org/r/20220824112124.21675-1-pali@kernel.orgSigned-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

driver_register() will refuse to register another driver with the same name.
This change allows pcie-mediatek-gen3 to coexist with pcie-mediatek built into
the kernel.

Link: https://lore.kernel.org/r/20220505083907.86598-1-nbd@nbd.name
Fixes: d3bf75b5 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192")
Signed-off-by: NFelix Fietkau <nbd@nbd.name>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: NJianjun Wang <jianjun.wang@mediatek.com>

PCI emul bridge members iolimitupper, iobaseupper, memlimit and membase
are of type __le16, so correctly access these members using
le16_to_cpu() macros.

Link: https://lore.kernel.org/r/20220812141115.24082-1-pali@kernel.org
Fixes: e7a01876 ("PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers")
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>

Sort the device-id table entries alphabetically by compatible string to
make it easier to find entries and add new ones.

Link: https://lore.kernel.org/r/20220714071348.6792-9-johan+linaro@kernel.orgSigned-off-by: NJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NBrian Masney <bmasney@redhat.com>
Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com>

The various IP versions have different configurations that are encoded
in separate sets of operation callbacks. Currently, there is no need for
also maintaining corresponding sets of data parameters, but it is
conceivable that these may again be found useful (e.g. to implement
minor variations of the operation callbacks).

Rename the default configuration structures after the IP version they
apply to so that they can more easily be reused by different SoCs.

Note that SoC specific configurations can be added later if need arises
(e.g. cfg_sc8280xp).

Link: https://lore.kernel.org/r/20220714071348.6792-8-johan+linaro@kernel.orgSigned-off-by: NJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBrian Masney <bmasney@redhat.com>
Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com>

The kernel is not a devicetree validator and does not need to re-encode
information which is already available in the devicetree.

This is specifically true for the optional PCIe clocks, some of which
are really interconnect clocks.

Treat also the 2.7.0 optional clocks as truly optional instead of
maintaining a list of clocks per compatible (including two compatible
strings for the two identical controllers on sm8450) just to validate
the devicetree.

Link: https://lore.kernel.org/r/20220714071348.6792-7-johan+linaro@kernel.orgSigned-off-by: NJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: NBrian Masney <bmasney@redhat.com>
Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com>

The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane
and one 1-lane.

Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops.

Note that like for SC8280XP, the SA8540P controllers need two or three
interconnect clocks to be enabled.

Link: https://lore.kernel.org/r/20220714071348.6792-6-johan+linaro@kernel.orgSigned-off-by: NJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: NBrian Masney <bmasney@redhat.com>
Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com>

The SC8280XP platform has seven PCIe controllers: two used with USB4,
two 4-lane, two 2-lane and one 1-lane.

Add a new "qcom,pcie-sc8280xp" compatible string and reuse the 1.9.0
ops.

Note that the SC8280XP controllers need two or three interconnect
clocks to be enabled. Model these as optional clocks to avoid encoding
devicetree data in the PCIe driver.

Note that the same could be done for the SM8450 interconnect clocks and
possibly also for the TBU clocks.

Link: https://lore.kernel.org/r/20220714071348.6792-5-johan+linaro@kernel.orgSigned-off-by: NJohan Hovold <johan+linaro@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: NStanimir Varbanov <svarbanov@mm-sol.com>

With Broadcom Broadband arch ARCH_BCMBCA supported in the kernel, this
patch series migrate the ARCH_BCM4908 symbol to ARCH_BCMBCA. Hence
replace ARCH_BCM4908 with ARCH_BCMBCA in subsystem Kconfig files.
Signed-off-by: NWilliam Zhang <william.zhang@broadcom.com>
Acked-by: Guenter Roeck <linux@roeck-us.net> (for watchdog)
Acked-by: Bjorn Helgaas <bhelgaas@google.com> (for drivers/pci)
Acked-by: Wolfram Sang <wsa@kernel.org> (for i2c)
Acked-by: Philipp Zabel <p.zabel@pengutronix.de> (for reset)
Link: https://lore.kernel.org/r/20220803175455.47638-7-william.zhang@broadcom.comSigned-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

ntb_mw_set_trans() will set memory map window after endpoint function
driver bind. The inbound map address need be updated dynamically when
using NTB by PCIe Root Port and PCIe Endpoint connection.

Checking if iatu already assigned to the BAR, if yes, using assigned iatu
number to update inbound address map and skip set BAR's register.
Signed-off-by: NFrank Li <Frank.Li@nxp.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Support more than Gen2 speed link mode, since i.MX8MP PCIe supports up to
Gen3 link speed.

Link: https://lore.kernel.org/r/1658287576-26908-1-git-send-email-hongxing.zhu@nxp.comSigned-off-by: NRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The PCIE_DBI_RO_WR_EN bit should be set when write some DBI registers.  To
make sure that the DBI registers are writable, set the PCIE_DBI_RO_WR_EN
properly when writing the DBI registers.

Link: https://lore.kernel.org/r/1652866528-13220-1-git-send-email-hongxing.zhu@nxp.comSigned-off-by: NRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Create imx6_pcie_stop_link() and imx6_pcie_host_exit() functions.
Encapsulate clocks, regulators disables and PHY uninitialization into
imx6_pcie_host_exit().

To keep suspend/resume symmetric as much as possible, invoke these two
new created functions in suspend callback.

To be symmetric with imx6_pcie_host_exit(), move imx6_pcie_clk_enable()
to imx6_pcie_host_init() from imx6_pcie_deassert_core_reset().

Link: https://lore.kernel.org/r/1657783869-19194-18-git-send-email-hongxing.zhu@nxp.comSigned-off-by: NRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLucas Stach <l.stach@pengutronix.de>

Move the imx6_pcie_ltssm_disable() earlier and place it just behind the
imx6_pcie_ltssm_enable(), since it might not be only used by suspend
callback directly.

To be symmetric with imx6_pcie_ltssm_enable(), add the IMX6Q and IMX8MQ
switch cases in imx6_pcie_ltssm_disable().

Link: https://lore.kernel.org/r/1657783869-19194-17-git-send-email-hongxing.zhu@nxp.comSigned-off-by: NRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

imx6_pcie_clk_enable() enables clocks in the order:

  pcie_phy
  pcie_bus
  pcie
  imx6_pcie_enable_ref_clk

Change imx6_pcie_clk_disable() to disable them in the reverse order.

Link: https://lore.kernel.org/r/1657783869-19194-16-git-send-email-hongxing.zhu@nxp.comSigned-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NRichard Zhu <hongxing.zhu@nxp.com>