Add cpuidle support for i.MX6SL, currently only support
two cpuidle levels(ARM wfi and WAIT mode), and add software
workaround for WAIT mode errata as below:

ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
          during WAIT mode entry process could cause cache memory
          corruption.

Software workaround:
    To prevent this issue from occurring, software should ensure that
the ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
entering WAIT mode.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The reset value of AHB divider is 3, so current AHB rate
is 99MHz which is not correct for kernel, need to ensure
AHB rate is 132MHz in clk driver, as ipg is sourcing from
AHB, and it should be 66MHz by default.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Bit 17 of register CCM_CGPR is called INT_MEM_CLK_LPM as per the mx6
reference manual, so use this name instead.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

MULTI_V6 should default to V6K as it is more optimal than V6. Any
platform which is not V6K should select CPU_V6 which will enable the
less optimal code paths.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Anton Vorontsov <anton@enomsg.org>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Jamie Iles <jamie@jamieiles.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Many V6 and V7 platforms have an L2x0 cache, so make
CONFIG_MIGHT_HAVE_CACHE_L2X0 visible for V6 and V7 multi-platform
builds.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7
multi-platform builds.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Multi-platform requires various kconfig options to be selected, so
platforms don't need to select them individually.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

When building a kernel image with only CONFIG_CPU_IDLE but no CONFIG_PM,
we will get the following link error.

  LD      init/built-in.o
arch/arm/mach-imx/built-in.o: In function `imx6q_enter_wait':
platform-spi_imx.c:(.text+0x25c0): undefined reference to `imx6q_set_lpm'
platform-spi_imx.c:(.text+0x25d4): undefined reference to `imx6q_set_lpm'
arch/arm/mach-imx/built-in.o: In function `imx6q_cpuidle_init':
platform-spi_imx.c:(.init.text+0x75d4): undefined reference to `imx6q_set_chicken_bit'
make[1]: *** [vmlinux] Error 1

Since pm-imx6q.c has been a collection of library functions that access
CCM low-power registers used by not only suspend but also cpuidle and
other drivers, let's build pm-imx6q.c independently of CONFIG_PM to fix
above error.
Reported-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: stable@vger.kernel.org
Acked-by: NChristian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Since commit 9e8147bb
"ARM: imx6q: move low-power code out of clock driver"
the kernel fails to boot on i.MX6Q/D if preemption is
enabled (CONFIG_PREEMPT=y). The kernel just hangs
before the console comes up.

The above commit moved the initalization of the low-power
mode setting (enabling clocked WAIT states), which was
introduced in commit 83ae2098
"ARM: imx: correct low-power mode setting", from
imx6q_clks_init to imx6q_pm_init. Now it is called
much later, after all cores are enabled.

This patch moves the low-power mode initialization back
to imx6q_clks_init again (and to imx6sl_clks_init).
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

LED platform data are overwhelmed by excessive field "max_cur"
which just replicates few bits of "led_control" field.
This patch removes this field and adds a definition for the
current settings in the header.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NBryan Wu <cooloney@gmail.com>

Add support for the SolidRun HummingBoard.  This commit adds support for
the following interfaces on this board:

- Consumer Ir receiver
- S/PDIF output
- Both USB interfaces
- Gigabit Ethernet using AR8035
- UART port
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

warning: (ARCH_MULTIPLATFORM && ARCH_CLPS711X && ARCH_PXA &&
 SOC_EXYNOS5440 && ARCH_EMEV2) selects AUTO_ZRELADDR which
 has unmet direct dependencies (!ZBOOT_ROM)

This is because it's possible to have ZBOOT_ROM enabled, but at the
same time have another option enabled which selects AUTO_ZRELADDR
overriding the !ZBOOT_ROM dependency.  Fix this by reversing the
dependencies between ZBOOT_ROM and the options which depend on
!ZBOOT_ROM.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Improve the comment of SW workaround for CCM lpm issue using
hardware errata description to avoid confusion.

ERR007265: CCM: When improper low-power sequence is used, the SoC
enters low power mode before the ARM core executes WFI.

Software workaround:
1) Software should trigger IRQ #32 (IOMUX) to be always pending
   by setting IOMUX_GPR1_GINT.
2) Software should then unmask IRQ #32 in GPC before setting CCM
   Low-Power mode.
3) Software should mask IRQ #32 right after CCM Low-Power mode is
   set (set bits 0-1 of CCM_CLPCR).
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

For ccm clock gate, both 2b'11 and 2b'01 should be treated
as clock enabled, see below description in CCM, whenver CPU
trys to check clock gate's status, system will be in run mode.

2b'00: clock is off during all modes;
2b'01: clock is on in run mode, but off in wait and stop mode;
2b'10: Not applicable;
2b'11: clock is on during all modes, except stop mode.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Common clk framework will disable unused clks in late init only if
they are enabled by default and no one is using it, so we need to
add is_enabled callback for clk framework to get clks' status.

PFD clocks are enabled by hardware reset, so we need to add
interface for common clk framework to disable those unused ones for
saving power.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Re-using iMX6Q driver for cpu frequency scaling.
Signed-off-by: NJohn Tobias <john.tobias.ph@gmail.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Cc: linux-arm-kernel@lists.infradead.org
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NDenis Carikli <denis@eukrea.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We are missing spba clock in imx6sl's clock tree, thus add it.
Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

There's a dividor for pll4_audio clock missing in clock tree, thus add it.
Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.
Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

0-DAY kernel build testing backend reports the following.

 scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch
 # many are suggestions rather than must-fix

 ERROR: Use of const init definition must use __initconst
 #80: arch/arm/mach-imx/mach-imx50.c:26:
 +static const char *imx50_dt_board_compat[] __initdata = {

While at it, fix the error globally for IMX platform.
Reported-by: NFengguang Wu <fengguang.wu@intel.com>
Acked-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

ldb_di0_gate is registerd with the clk index of IMX5_CLK_LDB_DI1_GATE,
thus the DI0 interface will be turned off inadvertently during boot.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Reviewed-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.

In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
is a just sign bit. This patch makes different calculation for i.MX27.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

According to the i.MX50 Rev. 1 and i.MX53 Rev. 2.1 datasheet the lp_apm_sel is
bit 10 in the CCM_CCSR register not bit 9. On the i.MX51 it's bit 9.

This patch fixes this issue.
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this
patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA
driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to
work correctly.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Linux-IDE <linux-ide@vger.kernel.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The macro name IMX6SL_CLK_CLK_END is a little insane.  Rename it to
IMX6SL_CLK_END.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Instead of selecting PINCTRL on individual SoC, let's select it at IMX
sub-architecure level.

While at it, it also adds the missing PINCTRL_IMX50 selection for
SOC_IMX50.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

ARM clock is sourcing from pll1_sw, and pll1_sw can be either from
pll1_sys or step, so we should enable arm clock during clock
initialization instead of pll1_sys, otherwise, arm clock's usecount
would be incorrect and PLL1 will never be disabled even it is not
used.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Use clock defines in order to make devicetrees more
human readable.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Correct spelling typo in various part of kernel
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Acked-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

We have a handy macro to replace open coded __cpuc_flush_dcache_area(()
and outer_clean_range() sequences. Let's use it. No functional change.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NJingchang Lu <b35083@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Patch adds missing Security Accelerator (SAHARA) clock for i.MX5x CPUs.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: NDenis Carikli <denis@eukrea.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Remove duplicated include.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add machine support code for the Freescale IMX50 SoC.

The IMX50 is quite similar to the Freescale IMX53, and contains many of the
same periperhal hardware modules, at the same address offsets as the IMX53.
(Notable exceptions are that the IMX50 contains no CAN bus hardware, less
GPIO, no VPU, it does contain an Electrophoretic display controller though).

This support code uses some of the IMX53 setup code to reduce duplication
of what would be identical init IO setup.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The code for irq priorisation support doesn't have any in-tree users and
the Kconfig description does wrong promises because nowadays irq
handlers are called with irqs disabled, so no high prioritized irq can
interrupt a lower prioritized handler.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Today, imx53 handles iomux configuration using pinctrl driver, so
mxc_iomux_v3_init() call in imx53_init_early() is there for nothing.
Remove the call from there.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>