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  1. 26 9月, 2013 2 次提交
  3. 28 8月, 2013 1 次提交
  5. 07 8月, 2013 7 次提交
  7. 30 7月, 2013 2 次提交
  9. 27 7月, 2013 1 次提交
  11. 15 7月, 2013 1 次提交
    • P
      arm: delete __cpuinit/__CPUINIT usage from all ARM users · 8bd26e3a
      由 Paul Gortmaker 提交于 
      The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications.  For example, the fix in
commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out.  Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit  -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings.  In any case, they are temporary and harmless.

This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code.  It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.

[1] https://lkml.org/lkml/2013/5/20/589

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      8bd26e3a
  13. 25 6月, 2013 7 次提交
  15. 13 6月, 2013 2 次提交
  17. 31 5月, 2013 3 次提交
  19. 23 5月, 2013 1 次提交
  21. 16 5月, 2013 1 次提交
  23. 08 5月, 2013 1 次提交
  25. 19 4月, 2013 1 次提交
  27. 12 4月, 2013 1 次提交
    • S
      ARM: msm: Fix uncompess.h tx underrun check · 73a8c28f
      由 Stephen Boyd 提交于 
      Bit 3 of the SR register is set if there is a tx underrun. If
this bit isn't set, we should loop on the tx ready bit until we
can transmit again. Otherwise we should skip the loop and
transmit immediately. The code is doing the opposite though,
checking for an underrun and then looping on the tx ready bit
causing us to never loop on the tx read bit when the tx buffer
may not be ready.

This doesn't seem to affect my 8960 device too often, but in some
cases I see a lost character or two from the decompressor prints.
This also matches what we do in the assembly in debug-macro.S.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
      73a8c28f
  29. 10 4月, 2013 2 次提交
  31. 27 3月, 2013 1 次提交
  33. 23 3月, 2013 3 次提交
    • S
      ARM: msm: Wait for timer clear to complete · e25e3d1f
      由 Stephen Boyd 提交于 
      Without looping on the status bit, there is no way to guarantee
that a clear of the timer has actually completed. This can cause
us to enable the timer before the count has cleared and miss a
timer interrupt. To simplify this patch, remove the timer
register setup done during timer init, since it's duplicate work
that is eventually done in the set_next_event() callback.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
      e25e3d1f
    • S
      ARM: msm: Rework timer binding to be more general · eebdb0c1
      由 Stephen Boyd 提交于 
      The msm timer binding I wrote is bad. First off, the clock
frequency in the binding for the dgt is wrong. Software divides
down the input rate by 4 to achieve the rate listed in the
binding. We also treat each individual timer as a separate
hardware component, when in reality there is one timer block
(that may be duplicated per cpu) with multiple timers within it.
Depending on the version of the hardware there can be one or two
general purpose timers, status and divider control registers, and
an entirely different register layout.

In the next patch we'll need to know about the different register
layouts so that we can properly check the status register after
clearing the count. The current binding makes this complicated
because the general purpose timer's reg property doesn't indicate
where that status register is, and in fact it is beyond the size
of the reg property.

Clean all this up by just having one node for the timer hardware,
and describe all the interrupts and clock frequencies supported
while having one reg property that covers the entire timer
register region. We'll use the compatible field in the future to
determine different register layouts and if we should read the
status registers, etc.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
      eebdb0c1
    • S
      ARM: msm: Stop counting before reprogramming clockevent · 4080d2d1
      由 Stephen Boyd 提交于 
      If the clockevent is forcibly reprogrammed to have a different
match value we mistakenly assume the timer is not ticking and
program a new match value while the timer is running. Although we
clear the timer before programming a new match, it's better to
stop the timer before clearing it so that we're sure the proper
amount of ticks are counted. Failure to do so can lead to missed
ticks and system hangs.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
      4080d2d1
  35. 06 3月, 2013 3 次提交