1. 23 5月, 2019 1 次提交
    • V
      cxgb4: Enable hash filter with offload · 74dd5aa1
      Vishal Kulkarni 提交于
      Hash (exact-match) filters used for offloading flows share the
      same active region resources on the chip with upper layer drivers,
      like iw_cxgb4, chcr, etc. Currently, only either Hash filters
      or ULDs can use the active region resources, but not both. Hence,
      use the new firmware configuration parameters (when available)
      to allow both the Hash filters and ULDs to share the
      active region simultaneously.
      Signed-off-by: NVishal Kulkarni <vishal@chelsio.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      74dd5aa1
  2. 02 3月, 2019 1 次提交
  3. 15 2月, 2019 1 次提交
    • V
      cxgb4/cxgb4vf: Add support for SGE doorbell queue timer · d429005f
      Vishal Kulkarni 提交于
      T6 introduced a Timer Mechanism in SGE called the
      SGE Doorbell Queue Timer. With this we can now configure
      TX Queues to get CIDX Updates when:
      
          Time(CIDX == PIDX) >= Timer
      
      Previously we rely on TX Queue Status Page updates by hardware
      for DMA completions. This will make Hardware/Firmware actually
      deliver the CIDX Updates as Ingress Queue messages with
      commensurate Interrupts.
      
      So we now have a new RX Path component for processing CIDX Updates
      and reclaiming TX Descriptors faster.
      
      Original work by: Casey Leedom <leedom@chelsio.com>
      Signed-off-by: NVishal Kulkarni <vishal@chelsio.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d429005f
  4. 24 11月, 2018 1 次提交
  5. 10 10月, 2018 1 次提交
  6. 08 9月, 2018 1 次提交
  7. 12 7月, 2018 1 次提交
  8. 01 6月, 2018 1 次提交
  9. 24 5月, 2018 1 次提交
  10. 15 5月, 2018 1 次提交
  11. 12 5月, 2018 1 次提交
  12. 01 4月, 2018 1 次提交
  13. 22 3月, 2018 3 次提交
  14. 13 3月, 2018 1 次提交
  15. 24 1月, 2018 1 次提交
  16. 11 1月, 2018 1 次提交
  17. 29 12月, 2017 1 次提交
  18. 14 12月, 2017 1 次提交
  19. 29 11月, 2017 1 次提交
  20. 01 11月, 2017 1 次提交
  21. 27 10月, 2017 1 次提交
  22. 20 10月, 2017 1 次提交
  23. 21 8月, 2017 1 次提交
  24. 21 7月, 2017 1 次提交
  25. 05 7月, 2017 1 次提交
  26. 24 6月, 2017 1 次提交
  27. 10 6月, 2017 1 次提交
  28. 22 5月, 2017 1 次提交
  29. 09 5月, 2017 1 次提交
  30. 21 4月, 2017 1 次提交
  31. 03 2月, 2017 1 次提交
  32. 08 10月, 2016 2 次提交
    • S
      iw_cxgb4: add fast-path for small REG_MR operations · 49b53a93
      Steve Wise 提交于
      When processing a REG_MR work request, if fw supports the
      FW_RI_NSMR_TPTE_WR work request, and if the page list for this
      registration is <= 2 pages, and the current state of the mr is INVALID,
      then use FW_RI_NSMR_TPTE_WR to pass down a fully populated TPTE for FW
      to write.  This avoids FW having to do an async read of the TPTE blocking
      the SQ until the read completes.
      
      To know if the current MR state is INVALID or not, iw_cxgb4 must track the
      state of each fastreg MR.  The c4iw_mr struct state is updated as REG_MR
      and LOCAL_INV WRs are posted and completed, when a reg_mr is destroyed,
      and when RECV completions are processed that include a local invalidation.
      
      This optimization increases small IO IOPS for both iSER and NVMF.
      Signed-off-by: NSteve Wise <swise@opengridcomputing.com>
      Signed-off-by: NDoug Ledford <dledford@redhat.com>
      49b53a93
    • S
      cxgb4: advertise support for FR_NSMR_TPTE_WR · 086de575
      Steve Wise 提交于
      Query firmware for the FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR parameter.
      If it exists and is 1, then advertise support for FR_NSMR_TPTE_WR to
      the ULDs.
      Signed-off-by: NSteve Wise <swise@opengridcomputing.com>
      Signed-off-by: NDoug Ledford <dledford@redhat.com>
      086de575
  33. 21 9月, 2016 1 次提交
  34. 23 8月, 2016 1 次提交
  35. 19 8月, 2016 2 次提交
  36. 26 7月, 2016 1 次提交