By moving all dev_vdbg() to tracepoints, we
can finally get rid of dev_vdbg() usage from
dwc3.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

as it turns out, at least AM437x silicon (non-FPGA)
needs to enable PHY suspend quirk. So let's allow
for PHY suspend quirk to be used with non-FPGA
builds too.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

HIRD threshold should be configurable by different platforms.

From DesignWare databook:
When HIRD_Threshold[4] is set to 1b1 and HIRD value is greater than or
equal to the value in HIRD_Threshold[3:0], dwc3 asserts output signals
utmi_l1_suspend_n to put PHY into Deep Low-Power mode in L1.

When HIRD_Threshold[4] is set to 1b0 or the HIRD value is less than
HIRD_Threshold[3:0], dwc3 asserts output signals utmi_sleep_n on L1.
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds disable usb2 suspend phy quirk, and some special platforms
can configure that if it is needed.
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds disable usb3 suspend phy quirk, and some special platforms
can configure that if it is needed.
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds Tx de-emphasis quirk, and the Tx de-emphasis value is
configurable according to PIPE3 specification.

Value		Description
0		-6dB de-emphasis
1		-3.5dB de-emphasis
2		No de-emphasis
3		Reserved

It can be configured on DT or platform data.
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

It is recommended to set USB3 and USB2 SUSPHY bits to '1' after the core
initialization is completed above the dwc3 revision 1.94a.
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds RX_DETECT to Polling.LFPS control quirk, and some special
platforms can configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds LFPS filter quirk, and some special platforms can configure
that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds delay PHY power change from P0 to P1/P2/P3 when link state
changing from U0 to U1/U2/U3 respectively, and some special platforms can
configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds delay P0 to P1/P2/P3 quirk for U2/U2/U3, and some special
platforms can configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds request P1/P2/P3 quirk for U2/U2/U3, and some special
platforms can configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds P3 in U2 SS inactive quirk, and some special platforms can
configure that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds u2exit lfps quirk, and some special platforms can configure
that if it is needed.

[ balbi@ti.com : added DeviceTree binding documentation ]
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced
Configuration of coreConsultant, it supports of xHCI BESL Errata Dated
10/19/2011 is enabled in host mode. In device mode it adds the capability
to send NYET response threshold based on the BESL value received in the LPM
token, and the threhold is configurable for each soc platform.

This patch adds an entry that soc platform is able to define the lpm
capacity with their own device tree or bus glue layer.

[ balbi@ti.com : added devicetree documentation, spelled threshold
		completely, made sure threshold is only applied to
		proper core revisions. ]
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch adds disscramble quirk, and it only needs to be enabled at fpga
board on some vendor platforms.
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Some chip vendor is on pre-silicon phase, which needs to use the simulation
board. It should have the same product and vendor id with the true soc, but
might have some minor different configurations.

Below thread discussion proposes to find a method to distinguish between
simulation board and soc.

http://marc.info/?l=linux-usb&m=141194772206369&w=2

In Andvanced Configuration of coreConsultant, there is the parameter of
DWC_USB_EN_FPGA. This bit has the function we need. And it would response as 7
bit of GHWPARAMS6 register. So it's able to check this functional bit to confirm
if works on FPGA board.
Reported-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

It enables hibernation if the function is set in coreConsultant.
Suggested-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Using ->prepare()/->complete() to mask/unmask
IRQs is wrong at least for dwc3. We need to
make sure that by the end of ->resume(), IRQs
are working and ready to fire because a child
device may need working IRQs for its own ->resume()
method.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Adding ACPI ID used on newer Intel SoCs.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

If the probe drivers have already set the dma_mask, not
replacing the value.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

DWC3's GUID register is supposed to be used to write
any sort of version we might want. It helps when getting
bug reports for platforms you don't have HW to know
which kernel version of the driver was running on the
platform.

Because we don't really track driver version, but we _do_
track the kernel version, let's write LINUX_VERSION_CODE to
that register and use it for debugging.
Reviewed-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

We can't suspend the PHYs before dwc3_core_exit_mode()
has been called, that's because the host and/or device
sides might still need to communicate with the far end
link partner.

Fixes: 8ba007a9 (usb: dwc3: core: enable the USB2 and USB3 phy in probe)
Cc: <stable@vger.kernel.org> # v3.9+
Suggested-by: NAlan Stern <stern@rowland.harvard.edu>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Currently, we disable pm_runtime before all register
accesses are done, this is dangerous and might lead
to abort exceptions due to the driver trying to access
a register which is clocked by a clock which was long
gated.

Fix that by moving pm_runtime_put_sync() and pm_runtime_disable()
as the last thing we do before returning from our ->remove()
method.

Fixes: 72246da4 (usb: Introduce DesignWare USB3 DRD Driver)
Cc: <stable@vger.kernel.org> # v3.2+
Signed-off-by: NFelipe Balbi <balbi@ti.com>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Newer DWC3 controllers can be built for USB 2.0-only mode, where
most of the USB 3.0 circuitry is left out. To support this mode,
the driver must limit the speed programmed into the DCFG register
to Hi-Speed or lower.

Reads and writes to the PIPECTL register are left as-is, since
they should be no-ops in USB 2.0-only mode. Calls to phy_init()
etc. for the USB3 phy are also left as-is, since the no-op USB3
phy should be used for USB 2.0-only mode controllers.
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Putting together the code related to getting the 'IORESOURCE_MEM'
and assigning the same to dwc->xhci_resources, for increasing
the readability.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

First usage of ret variable will re-write initial value. Thus, there is no need
to initialize it.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Move mode (Host, Peripheral, OTG) initialization
to its own function in order to decrease the size
of our probe() routine.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

our probe() routine is too large and we can
easily refactor PHY-related code out to another
function to make it slightly less painful to read.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

During system resume, if the event buffers are not setup before
the gadget controller starts then we start with invalid context
and this can lead to bus access errors. This is especially true for
platforms that loose the controller context during system suspend.
e.g. AM437x.

The following backtrace was found when the system is suspended
and resumed with g_zero loaded on AM437x-evm (USB cable connected
to host all the while).

[  120.981506] WARNING: CPU: 0 PID: 1656 at drivers/bus/omap_l3_noc.c:137 l3_interrupt_handler+0x198/0x28c()
[  120.981514] L3 custom error: MASTER:USB0 WR TARGET:GPMC
[  120.981638] Modules linked in: g_mass_storage usb_f_mass_storage libcomposite configfs bufferclass_ti(O) omaplfb(O) cryptodev(O) dwc3 snd_soc_evm snd_soc_omap snd_pe
[  120.981659] CPU: 0 PID: 1656 Comm: sh Tainted: G           O 3.12.10-gc559824 #1
[  120.981669] Backtrace:
[  120.981705] [<c0017880>] (dump_backtrace+0x0/0x10c) from [<c0017a1c>] (show_stack+0x18/0x1c)
[  120.981730]  r6:c02819ac r5:00000009 r4:ec137cb8 r3:00000000
[  120.981767] [<c0017a04>] (show_stack+0x0/0x1c) from [<c056c0b0>] (dump_stack+0x20/0x28)
[  120.981802] [<c056c090>] (dump_stack+0x0/0x28) from [<c0046d08>] (warn_slowpath_common+0x70/0x90)
[  120.981830] [<c0046c98>] (warn_slowpath_common+0x0/0x90) from [<c0046dcc>] (warn_slowpath_fmt+0x38/0x40)
[  120.981856]  r8:c0855eb0 r7:00000002 r6:f1000700 r5:00000007 r4:80080003
[  120.981886] [<c0046d94>] (warn_slowpath_fmt+0x0/0x40) from [<c02819ac>] (l3_interrupt_handler+0x198/0x28c)
[  120.981900]  r3:c0801ab8 r2:c06cb354
[  120.981936] [<c0281814>] (l3_interrupt_handler+0x0/0x28c) from [<c007162c>] (handle_irq_event_percpu+0x54/0x1b8)
[  120.981962] [<c00715d8>] (handle_irq_event_percpu+0x0/0x1b8) from [<c00717c0>] (handle_irq_event+0x30/0x40)
[  120.981993] [<c0071790>] (handle_irq_event+0x0/0x40) from [<c0074058>] (handle_fasteoi_irq+0x74/0x128)
[  120.982006]  r4:ed0056c0 r3:00000000
[  120.982033] [<c0073fe4>] (handle_fasteoi_irq+0x0/0x128) from [<c0070f34>] (generic_handle_irq+0x28/0x38)
[  120.982046]  r4:0000002a r3:c0073fe4
[  120.982085] [<c0070f0c>] (generic_handle_irq+0x0/0x38) from [<c0015560>] (handle_IRQ+0x38/0x8c)
[  120.982098]  r4:c080137c r3:00000182
[  120.982124] [<c0015528>] (handle_IRQ+0x0/0x8c) from [<c00087e0>] (gic_handle_irq+0x30/0x5c)
[  120.982145]  r6:ec137dd0 r5:c07ac480 r4:fa24010c r3:00000100
[  120.982169] [<c00087b0>] (gic_handle_irq+0x0/0x5c) from [<c056fcc0>] (__irq_svc+0x40/0x54)
[  120.982179] Exception stack(0xec137dd0 to 0xec137e18)
[  120.982195] 7dc0:                                     00000000 a00001d3 00000000 00000004
[  120.982216] 7de0: a0000153 ec1d9010 c080de90 ec137e30 c080debc 00000000 ed756e44 ec137e2c
[  120.982232] 7e00: ec137de0 ec137e18 bf1150e4 bf115474 60000153 ffffffff
[  120.982253]  r7:ec137e04 r6:ffffffff r5:60000153 r4:bf115474
[  120.982327] [<bf115438>] (dwc3_complete+0x0/0x40 [dwc3]) from [<c0338f50>] (dpm_complete+0xd4/0x19c)
[  120.982341]  r5:ed756e10 r4:ed756e64
[  120.982370] [<c0338e7c>] (dpm_complete+0x0/0x19c) from [<c0339034>] (dpm_resume_end+0x1c/0x20)
[  120.982400] [<c0339018>] (dpm_resume_end+0x0/0x20) from [<c006d4ec>] (suspend_devices_and_enter+0x118/0x33c)
[  120.982412]  r4:c0833da4 r3:00000000
[  120.982436] [<c006d3d4>] (suspend_devices_and_enter+0x0/0x33c) from [<c006d928>] (pm_suspend+0x218/0x254)
[  120.982458] [<c006d710>] (pm_suspend+0x0/0x254) from [<c006c594>] (state_store+0x70/0xc0)
[  120.982478]  r6:c057a6cc r5:c06a8320 r4:00000003 r3:0000006d
[  120.982515] [<c006c524>] (state_store+0x0/0xc0) from [<c0264cc0>] (kobj_attr_store+0x1c/0x28)
[  120.982546] [<c0264ca4>] (kobj_attr_store+0x0/0x28) from [<c012ccb8>] (sysfs_write_file+0x170/0x1a4)
[  120.982583] [<c012cb48>] (sysfs_write_file+0x0/0x1a4) from [<c00d17e4>] (vfs_write+0xb8/0x190)
[  120.982611] [<c00d172c>] (vfs_write+0x0/0x190) from [<c00d1bf8>] (SyS_write+0x44/0x78)
[  120.982641] [<c00d1bb4>] (SyS_write+0x0/0x78) from [<c0014660>] (ret_fast_syscall+0x0/0x30)
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Adapted dwc3 core to use the Generic PHY Framework. So for init, exit,
power_on and power_off the following APIs are used phy_init(), phy_exit(),
phy_power_on() and phy_power_off().

However using the old USB phy library wont be removed till the PHYs of all
other SoC's using dwc3 core is adapted to the Generic PHY Framework.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Since PHYs for dwc3 is optional (not all SoCs having PHYs for DWC3
should be programmed), do not return from probe if the USB PHY library
returns -ENODEV as that indicates the platform does not have a
programmable PHY.

While this can be considered as a temporary fix, a long term solution
would be to add 'nop' PHY for platforms that does not have programmable
PHY.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

We must read HWPARAMS4 register to figure out
how many scratch buffers we should allocate.

Later patch will use "Set Scratchpad Buffer
Array" command to pass the pointer to the
IP so it can be used during hibernation.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Revisions between 2.10a and 2.50a (included) have
a known issue which may cause xHCI compliance tests
to fail and/or quality issues with Isochronous
transactions.

Note that this issue only impacts certain configurations
of those revisions, namely the ones which have clock
gating enabled.

The suggested workaround is to disable clock gating in
known broken revisions, make sure HW LPM is disabled
and set GCTL.SOFITPSYNC to 1.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

usb phy was power'ed on but was never power'ed off in the error path.
Fix it.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

usb_phy_set_suspend(phy, 0) is called before usb_phy_init. Fix it.
Reported-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

We are going to disable runtime_pm and we're
removing the driver, we must disable the device
now.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This delay got introduced in:
"7415f17c usb: dwc3: core: add power management support"
which reflected similar code in dwc3_core_soft_reset() function.
However, originally the delay of 100ms in dwc3_core_soft_reset() was
meant to assist USB2PHY and USB3PHY reset, not for usb_phy_init()
sequence.

We should get rid of this delay, since things will still work
fine without this.
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

otg.h header file was included twice.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NFelipe Balbi <balbi@ti.com>