1. 01 3月, 2018 14 次提交
  2. 19 12月, 2017 3 次提交
  3. 23 8月, 2017 1 次提交
    • T
      drm/omap: fix i886 work-around · 0c43f1e0
      Tomi Valkeinen 提交于
      7d267f06 ("drm/omap: work-around for
      errata i886") changed how the PLL dividers and multipliers are
      calculated. While the new way should work fine for all the PLLs, it
      breaks omap5 PLLs. The issues seen are rather odd: seemed that the
      output clock rate is half of what we asked. It is unclear what's causing
      there issues.
      
      As a work-around this patch adds a "errata_i886" flag, which is set only
      for DRA7's PLLs, and the PLL setup is done according to that flag.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      Tested-by: NH. Nikolaus Schaller <hns@goldelico.com>
      0c43f1e0
  4. 15 8月, 2017 8 次提交
  5. 02 6月, 2017 4 次提交
  6. 03 4月, 2017 5 次提交
  7. 01 3月, 2017 1 次提交
  8. 02 11月, 2016 2 次提交
  9. 20 5月, 2016 2 次提交